An apparatus and method for diagnosing a watchdog timer is provided. The watchdog timer is used to detect and recover from a malfunction of a battery management system. Before entering a shutdown mode in response to a shutdown command from an external device, the apparatus outputs an invalid trigger signal to the watchdog timer and diagnoses a malfunction of the watchdog timer depending on whether the watchdog timer outputs a reset signal.

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Systems and methods for simulation and testing of multiple virtual electronic control units (VECUs). A method (1000) includes executing, by one or more computer systems (101), a first VECU (502). The method includes executing a virtual bus (510), the virtual bus (510) associated with the first VECU (502). The method includes executing at least one second VECU. The method includes simulating a multiple-VECU system by managing communications, using the virtual bus (510), between the first VECU (502) and the at least one second VECU.

Certain aspects and features provide generation or simulation of sensory data that would otherwise come from Internet-of-things (IoT) sensors in reproducible and controllable way. Thus, the response of a system to very large numbers of sensors can be tested without acquiring and deploying a very large number of sensors for test and development purposes. In some examples, a processing device coupled to a network interface identifies a stored function of time describing a locally sensed property for a simulated sensor. The locally sensed property corresponds to at least one event taking place in a virtual environment. The processing device can determine values of an input variable produced by the stored function of time. The values can be wrapped in a communication protocol to produce messages that are transmitted over the network interface.

A system is provided for determining causes of faults in a manufacturing system. The system stores data associated with a processing system which includes machines and associated processes, wherein the data includes timestamp information, machine status information, and product-batch information. The system determines, based on the data, a topology of the processing system, wherein the topology indicates flows of outputs between the machines as part of the processes. The system determines information of machine faults in association with the topology. The system generates, based on the machine-fault information, one or more fault parameters which indicates frequency and severity of a respective fault. The system constructs, based on the topology and the machine-fault information, a system model which includes the one or more fault parameters, thereby facilitating diagnosis of the processing system.

Disclosed are hardware and techniques for testing computer processes in a network system by simulating computer process faults and identifying risk associated with correcting the simulated fault and identifying computer processes that may depend on the corrected computer process. The interdependent computer processes in a network may be determined by evaluating a risk matrix having a risk score and non-functional requirement score. An analysis of the risk score and non-functional requirement score accounts for interdependencies between computer processes and identified corrective actions that may be used to determine an optimal network environment. The optimal network environment may be updated dynamically based on changing computer process interdependencies and the determined risk and robustness scores.

Aspects of the invention include systems and methods for to detecting security vulnerabilities using modeled attribute propagation. A non-limited example of a computer-implemented method includes generating a model of a device under test, the model comprising a data path similar to the device under test and an attribute network. The method further includes detecting protected data that is introduced into the model and marking the protected data with an attribute. An end point of the marked protected data is detected along the data path. In response to the end point being indicative of a vulnerability, an alert is issued.

A fault injection system for a software system, wherein the software system includes executable commands, events generated by commands and states representing a state of a state machine between two events, wherein a fault injection rule database is configured to provide a rule for injecting a selected fault, wherein the rule provides a fault injection decision in the occurrence of a selected command, a selected state during which fault injection is to occur and a condition under which fault injection is to occur; an estimator module is configured to determine when the selected state will occur related to the execution of the selected command and to provide a duration of a state as a time interval for fault injection, wherein the determination is based on a predictive time model; and an injector module is configured to execute the selected command and to inject the selected fault during the time interval.

A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

A computer-implemented method according to one embodiment includes simulating, for a predetermined time period, output of a first task that periodically runs within a system to create a simulated output, comparing the simulated output to actual output of the first task for the predetermined time period, and generating an alert in response to determining that the simulated output does not match the actual output for the predetermined time period.