In general, a device comprising a processor and a memory may be configured to perform various aspects of the techniques described in this disclosure. The processor may conduct, based on configuration parameters, each of a plurality of simulation iterations within the test environment to collect a corresponding plurality of simulation datasets representative of operating states of the network device. The processor may perform a regression analysis with respect to each of the plurality of configuration parameters and each of the plurality of simulation datasets to generate a light weight model representative of the network device that predicts an operating state of the network device. The processor may output the light weight model for use in a computing resource restricted network device to enable prediction of the operating state of the computing resource restricted network device when configured with the configuration parameters. The memory may store the light weight model.

A virtual device acquires a transaction history between a legacy computing device and a linked device; obtains a first request provided from the legacy computing device based on the transaction history and a first response received from the linked device in response to the first request; receives a second request corresponding to the first request from a new computing device and determines a second response to the second request; and provides test information for the new computing device based on a comparison of the first response and the second response.

The invention relates to an apparatus and a system for debugging a solid-state disk (SSD) device. The apparatus includes a Joint Test Action Group (JTAG) add-on board; and a Raspberry Pi. The Raspberry Pi includes a General-Purpose Input/Output (GPIO) interface (I/F), coupled to the JTAG add-on board; and a processing unit, coupled to the GPIO I/F. The processing unit is arranged operably to: simulate to issue a plurality of JTAG command through the GPIO I/F to the SSD device for dumping data generated by the SSD device during operation from the SSD device.

A memory controller coupled to a memory device and configured to control access operations of the memory device includes a host interface and a microprocessor. The microprocessor is coupled to the host interface and configured to set a value of a predetermined parameter to a specific value after the memory controller powers up and start to perform a link flow to try to establish a transmission link via the host interface. The predetermined parameter is one of a plurality of capability parameters of the host interface and the predetermined parameter is related to reception of the host interface. After the link flow is completed, the microprocessor is further configured to identify an object device with which the host interface establishes the transmission link according to the specific value and at least one of a plurality of attribute parameters associated with the transmission link.

An error rate measuring apparatus detects a bit error of input data returned from a device under test with transmission of a test signal at an error detector, and includes a log recording unit that records log data of state transition of each lane by handshakes of a plurality of lanes in a predetermined communication standard with respect to the device under test in making the device under test transit to a state of LOOPBACK, and a display unit that displays the recorded log data of the state transition of each lane in a time-series order.

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor configured to execute a custom BMC firmware stack, and a second processor including executable instructions for receiving a request to perform a test on the first processor in which the request is received through a secure communication session established with a remote IHS. The instructions further perform the acts of controlling the first processor to perform the test according to the request, the first processor generating test results associated with the test, and transmitting the test results to the remote IHS through the secure communication session.

A variable power bus (VPB) cable, such as a USB Type-C cable, is validated for actual current capacity with respect to a specified power rating for the cable. The power cable validation is performed when the cable is connected to a power storage adapter and a portable information handling system. The validation includes, prior to negotiating a power delivery contract for electrical power to be supplied to the information handling system from the VPB port via the VPB cable, applying a first voltage to the VPB cable to identify a first indication of a current capacity of the VPB cable; and when the first indication confirms that the current capacity of the VPB cable corresponds to a specified power rating for the VPB cable, enabling the power delivery contract to be negotiated according to the specified power rating, otherwise blocking the power delivery contract using the VPB cable.

A network (101) is composed of a bus branched at one or more points, and one or more nodes are connected to each branch line. An inspection control unit (220) outputs a base signal. An amplification control unit (210) determines an amplification period and an amplification factor based on a parameter, and amplifies the base signal with the determined amplification factor during the determined amplification period. The inspection control unit (220) accepts, as an inspection signal, the base signal whose waveform has changed as a result of flowing though the bus, and judges whether or not there is a new node connected to the bus based on a waveform of the inspection signal.

A network (101) is composed of a bus branched at one or more points, and one or more nodes are connected to each branch line. An inspection control unit (220) outputs a base signal. An amplification control unit (210) determines an amplification period and an amplification factor based on a parameter, and amplifies the base signal with the determined amplification factor during the determined amplification period. The inspection control unit (220) accepts, as an inspection signal, the base signal whose waveform has changed as a result of flowing though the bus, and judges whether or not there is a new node connected to the bus based on a waveform of the inspection signal.

During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.