G06F11/273

Device maintenance apparatus, device maintenance method, and non-transitory computer readable storage medium

A device maintenance apparatus includes a test executor configured to cause a device to output an output signal based on a test pattern that changes the output signal output from the device with an elapse of time, and a change instructor configured to issue a change instruction for changing at least one of a progress of an output of the output signal based on the test pattern and an output value of the output signal to the test executor in accordance with an instruction input while the test executor causes the device to execute the output of the output signal.

Device diagnostic web system, device diagnostic method and program storage medium
11494279 · 2022-11-08 · ·

A device diagnostic web system that diagnoses a device locally connected to an information processing apparatus. In order to confirm whether or not access by the browser is to be permitted by connecting the device to the information processing apparatus via a local connection such as USB or Bluetooth, and executing a device diagnostic web application by a browser installed on this information processing apparatus, a confirmation screen for prompting a user to perform an operation of the information processing apparatus is displayed on the information processing apparatus, if the user permits the access, the device is communicatively connected to the browser to access the device and predetermined device information is acquired and diagnostic information is generated by using the acquired device information.

Leveraging low power states for fault testing of processing cores at runtime

In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

SYSTEMS, APPARATUSES, AND METHODS FOR AUTONOMOUS FUNCTIONAL TESTING OF A PROCESSOR
20230102991 · 2023-03-30 ·

Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.

SYSTEMS, APPARATUSES, AND METHODS FOR AUTONOMOUS FUNCTIONAL TESTING OF A PROCESSOR
20230102991 · 2023-03-30 ·

Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.

Hardware-controlled updating of a physical operating parameter for in-field fault detection

Latency of in-system test (IST) execution for a hardware component of an in-field (deployed) computing platform may be reduced when a value of a physical operating parameter can be changed without rebooting the computing platform. A test (e.g., patterns or vectors) is executed for varying values of the physical operating parameter (e.g., supply voltage, clock speed, temperature, noise magnitude/duration, operating current, and the like), providing the ability to detect faults in the hardware components.

Hardware-controlled updating of a physical operating parameter for in-field fault detection

Latency of in-system test (IST) execution for a hardware component of an in-field (deployed) computing platform may be reduced when a value of a physical operating parameter can be changed without rebooting the computing platform. A test (e.g., patterns or vectors) is executed for varying values of the physical operating parameter (e.g., supply voltage, clock speed, temperature, noise magnitude/duration, operating current, and the like), providing the ability to detect faults in the hardware components.

Software update on legacy system without application disruption

Methods and apparatus are disclosed to update software on a legacy system without disruption of live applications. In a database server environment, a nameserver restart can utilize a pre-existing hook facility to detect a newly introduced script and execute an initialization function of the script, leading to activation or launch of the script. In a use case of a high availability database server, the script can cause a copy of a replication status to be stored at a remote location. Upon failure of the database server, retrieval and verification of the replication status from the remote location enables failover to a replica server to be performed safely and automatically.

Software update on legacy system without application disruption

Methods and apparatus are disclosed to update software on a legacy system without disruption of live applications. In a database server environment, a nameserver restart can utilize a pre-existing hook facility to detect a newly introduced script and execute an initialization function of the script, leading to activation or launch of the script. In a use case of a high availability database server, the script can cause a copy of a replication status to be stored at a remote location. Upon failure of the database server, retrieval and verification of the replication status from the remote location enables failover to a replica server to be performed safely and automatically.

Apparatus, system, and method for achieving accurate insertion counts on removable modules
11489528 · 2022-11-01 · ·

A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.