Patent classifications
G06F11/273
Method, an all-in-one tester and computer program product
There are disclosed various methods, apparatuses and computer program products for a testing apparatus. In accordance with an embodiment the testing apparatus includes a frame; a gripping head for gripping a device to be tested; a first movement element for moving the gripping head with respect to the frame; a movement detector to detect at least one of a location and a position of the device; a touching element for touching the device; an imaging device for capturing images of the device; a display for generating visual information for capturing by the device; a set of sensors for examining operations of the device; a set of actuators for providing signals for reception by the device; and a set of plugs adapted to be inserted into a socket of the device.
Method, an all-in-one tester and computer program product
There are disclosed various methods, apparatuses and computer program products for a testing apparatus. In accordance with an embodiment the testing apparatus includes a frame; a gripping head for gripping a device to be tested; a first movement element for moving the gripping head with respect to the frame; a movement detector to detect at least one of a location and a position of the device; a touching element for touching the device; an imaging device for capturing images of the device; a display for generating visual information for capturing by the device; a set of sensors for examining operations of the device; a set of actuators for providing signals for reception by the device; and a set of plugs adapted to be inserted into a socket of the device.
API ADAPTER TEST SYSTEM, API ADAPTER TEST ASSISTANCE DEVICE, API ADAPTER TEST ASSISTANCE METHOD, AND API ADAPTER TEST ASSISTANCE PROGRAM
An API adapter test support system includes an API adapter test support apparatus (2), a user terminal simulation apparatus (50) and a user server simulation apparatus (60). The user terminal simulation apparatus and the user server simulation apparatus are connected to a wholesale service apparatus to which an API adapter. The API adapter test support apparatus includes a test scenario creation unit (32) configured to create a test scenario that ensures comprehensiveness of a test case of an API adapter test, a control signal test scenario execution unit (34) configured to execute a control signal API test for the API adapter by using the test scenario, and a data signal test scenario execution unit (41) configured to execute a data signal API test for the user terminal simulation apparatus (50) and the user server simulation apparatus (60) by using the test scenario.
API ADAPTER TEST SYSTEM, API ADAPTER TEST ASSISTANCE DEVICE, API ADAPTER TEST ASSISTANCE METHOD, AND API ADAPTER TEST ASSISTANCE PROGRAM
An API adapter test support system includes an API adapter test support apparatus (2), a user terminal simulation apparatus (50) and a user server simulation apparatus (60). The user terminal simulation apparatus and the user server simulation apparatus are connected to a wholesale service apparatus to which an API adapter. The API adapter test support apparatus includes a test scenario creation unit (32) configured to create a test scenario that ensures comprehensiveness of a test case of an API adapter test, a control signal test scenario execution unit (34) configured to execute a control signal API test for the API adapter by using the test scenario, and a data signal test scenario execution unit (41) configured to execute a data signal API test for the user terminal simulation apparatus (50) and the user server simulation apparatus (60) by using the test scenario.
Commanded JTAG test access port operations
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.
System and method for testing multi-user, multi-input/multi-output communication systems
A test system for testing a device under test includes: a signal processor configured to generate a plurality of independent signals and to apply first fading channel characteristics to each of the independent signals to generate a plurality of first faded test signals; a test system interface configured to provide the plurality of first faded test signals to one or more signal input interfaces of the device under test (DUT); a second signal processor configured to apply second fading channel characteristics to a plurality of output signals of the DUT to generate a plurality of second faded test signals, wherein the second fading channel characteristics are derived from the first fading channel characteristics; and one or more test instruments configured to measure at least one performance characteristic of the DUT from the plurality of second faded test signals.
TRACE BUFFER DATA MANAGEMENT
An emulation system traverses trace buffers to read data captured from a design under test (DUT). The emulation system receives a request to read at least a portion of DUT data. The emulation system reads a header of the latest sample of the DUT data, where header of each sample of the DUT data includes one or more pointers to a previously stored sample. The samples of the DUT data are partitioned into frames and sectors. The emulation system can identify samples of the DUT data using the pointers in the header of the samples and compare time stamps of the samples against a specified time stamp in the received request. After identifying a sample having the specified time stamp, the emulation system may read the sample for output to the user (e.g., reconstructing a waveform using the sample).
TRACE BUFFER DATA MANAGEMENT
An emulation system traverses trace buffers to read data captured from a design under test (DUT). The emulation system receives a request to read at least a portion of DUT data. The emulation system reads a header of the latest sample of the DUT data, where header of each sample of the DUT data includes one or more pointers to a previously stored sample. The samples of the DUT data are partitioned into frames and sectors. The emulation system can identify samples of the DUT data using the pointers in the header of the samples and compare time stamps of the samples against a specified time stamp in the received request. After identifying a sample having the specified time stamp, the emulation system may read the sample for output to the user (e.g., reconstructing a waveform using the sample).
LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES AT RUNTIME
In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.
Distributed Event-based Test Execution
Methods and computing devices for allocating test pods to a distributed computing system for executing a test plan on a device-under-test (DUT). Each test pod may include a test microservice including one or more test steps and an event microservice specifying function relations between the test microservice and other test microservices. The test pods are allocated to different servers to perform a distributed execution of the test plan on the DUT through one or more test interfaces.