G06F11/273

Distributed Event-based Test Execution

Methods and computing devices for allocating test pods to a distributed computing system for executing a test plan on a device-under-test (DUT). Each test pod may include a test microservice including one or more test steps and an event microservice specifying function relations between the test microservice and other test microservices. The test pods are allocated to different servers to perform a distributed execution of the test plan on the DUT through one or more test interfaces.

Automated hardware for input/output (I/O) test regression apparatus

A test apparatus is provided for use with a mainframe and an adapter. The test apparatus includes a logical adapter interface unit and a control system. The logical adapter interface unit is interposable between the adapter and the mainframe whereby an I/O signal transmittable from the adapter and to the mainframe is transmitted through the logical adapter interface unit. The logical adapter interface unit is configured to manipulate the I/O signal. The control system is coupled to the logical adapter interface unit and the mainframe and is configured to control manipulations of the I/O signal by the logical adapter interface unit to mimic a condition of I/O traffic being run through the adapter and to log a response of the mainframe to the manipulations.

SYSTEM AND METHOD FOR INTEGRATION TESTING

There is provided a system and method for performing system integration on an embedded system of a connected and/or autonomous vehicle. Integration testing may include obtaining one or more requirements and/or specifications for a system under test; generating a metamodel based on the requirements and/or specifications; generating test cases based on the metamodel; prioritizing said test cases based on hazards associated with said test cases; executing one or more of said prioritized test cases; and obtaining a verdict for each of said one or more prioritized test cases.

High-Frequency Event-Based Hardware Diagnostics
20220334939 · 2022-10-20 ·

An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.

High-Frequency Event-Based Hardware Diagnostics
20220334939 · 2022-10-20 ·

An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.

JTAG-Based Burning Device
20220317178 · 2022-10-06 ·

A JTAG-based burning device, comprising controllable switches provided between a TDI end of a JTAG host (1) and a first chip and between every two adjacent chips, and further comprising a main controllable switch module (2) provided between each chip and a TDO end of the JTAG host (1). According to a received burning instruction, the JTAG host (1) can control an input end of a corresponding controllable switch to be connected to a corresponding output end thereof, and also control an output end of the main controllable switch module (2) to be connected to a corresponding input end thereof. Hence, the device merely needs to build a circuit to automatically adjust a JTAG link by controlling the connection relationship between the input end and the output end of the corresponding switch, achieving burning of the firmware of different chips or a combination of chips, without manual adjustment, thereby improving the test efficiency, and simplifying a circuit structure.

PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
20220318109 · 2022-10-06 ·

A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.

In Vitro Neural Implant Tester with Hardware-in-the-Loop Simulation

Accelerated testing apparatuses for implants are described, as well as methods for accelerated testing implants. The accelerated testing apparatus includes a cabinet having multiple bays and a vessel insertable and removable from any of the multiple bays. The vessel includes a watertight basin, a radio-frequency (RF) transparent lid configured to mate with the basin, and a plurality of fixtures within the vessel. Each fixture is adapted to anchor a device-under-test while submersed within the vessel. The accelerated testing apparatus also includes a reservoir disposed within the cabinet, a heater connected with the reservoir, a pump configured to circulate liquid between the reservoir and the vessel, an antenna within the cabinet for communication with the device-under-test, and at least one computer server operatively connected with the antenna.

Fail-safe semi-autonomous or autonomous vehicle processor array redundancy which permits an agent to perform a function based on comparing valid output from sets of redundant processors
11645178 · 2023-05-09 · ·

Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.

Fail-safe semi-autonomous or autonomous vehicle processor array redundancy which permits an agent to perform a function based on comparing valid output from sets of redundant processors
11645178 · 2023-05-09 · ·

Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.