Devices and techniques for thread-based processor halting are described herein. A processor monitors control-status register (CSR) values that correspond to a halt condition for a thread. The processor then compares the halt condition to a current state of the thread and halts in response to the current state of the thread meeting the halt condition.

A device, such as a system on a chip (SoC), includes a plurality of processor cores, a broadcaster module, a plurality of decoder units, and an aggregator module. The broadcaster module broadcasts a debug request from a debugger device to one or more of the plurality of processor cores via a bus, the debug request including an address specifying a logical identifier associated with a target processor core of the plurality of processor cores. The decoder units, associated with the processor cores, forward the debug request to a debug module of the respective processor core in response to detecting a match. If no match is detected, the decoder units forward the debug request to a subsequent processor core via the bus. The aggregator module forward a response message to the debugger device, the response message originating from the target processor core.

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

A method and apparatus of monitoring computer devices operating on a network is disclosed. Computer devices are all different and require monitoring settings that are tailored to their specific requirements. One example of the present invention may include a method of monitoring at least one computer device operating on a network. The method may include receiving audit information representing attributes of the computer device and storing the audit information in memory. The method may also include comparing the audit information to a predefined monitor set of objects to be monitored. The method may further include creating a new monitor set based on the comparison of the audit information and the predefined monitor set. The new monitor set is different from the predefined monitor set and is generally used to monitor objects which are included in the audited device. The method may also include monitoring the at least one computer device based on the new monitor set.

Examples described herein relate to prefetching content from a remote memory device to a memory tier local to a higher level cache or memory. An application or device can indicate a time availability for data to be available in a higher level cache or memory. A prefetcher used by a network interface can allocate resources in any intermediary network device in a data path from the remote memory device to the memory tier local to the higher level cache. Memory access bandwidth, egress bandwidth, memory space in any intermediary network device can be allocated for prefetch of content. In some examples, proactive prefetch can occur for content expected to be prefetched but not requested to be prefetched.

The present disclosure may provide systems and methods for device parameter configuration. The systems may obtain a request for parameter configuration of a device. In response to receiving the request, the systems may acquire, from a first storage device, log data of the device. The log data may include data of one or more actual parameters indicating an operation of the device. The systems may also acquire, from a second storage device, data of one or more reference parameters of the device. The systems may obtain a comparison result by comparing the data of the one or more actual parameters and the data of the one or more reference parameters of the device. The systems may generate a feedback based on the comparison result.

The present disclosure relates to determining the shareability of values of node profiles. Record objects and electronic activities of a system of record corresponding to a data source provider may be accessed. Each record object may correspond to a record object type and have one or more object field-value pairs. Node profiles may be maintained. Values of fields corresponding to a predetermined type of field including fewer than a predetermined threshold number of data source providers may be identified. A restriction tag used to restrict populating other node profiles may be generated. Provision of the value with a second data source provider may be restricted.

Imposing and/or readjusting the CPU clocks for services of containers from various cloud-based cognitive systems in a multi-cloud cognitive computing environment for performing a particular job. The particular job having an emergency performance requirement. During processing of the job, a need to tune the execution of instructions is identified through a pre-existing emergency identification process that includes collecting clock data for each container supporting the performance of the particular job.

A chip frequency modulation method and apparatus of a computing device, a hash board, a computing device, and a storage medium are disclosed. The computing device is provided with at least one operational chip, and the operational chip is provided with a plurality of cores. The chip frequency modulation method includes: operating each of the plurality of cores in the operational chip configured with a plurality of frequencies to run at a working frequency, the working frequency being one of the plurality of frequencies; analyzing a computing performance indicator of each of the plurality of cores at the working frequency; and modulating a working frequency of at least one core up or down according to the computing performance indicator, a modulated working frequency being one of the plurality of frequencies.

A method, computer program product, and computing system for monitoring utilization of each central processing unit (CPU) core of a plurality of CPU cores. An average input/output (IO) latency for an operating system thread executing on the CPU core of the plurality of CPU cores may be determined. The operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core may be adjusted based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores.