An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

A system for monitoring inter-integrated circuit (12C) communication includes a power supply, a battery backup unit, an 12C serial clock line (SCL) coupled between the power supply and the battery backup unit, an 12C serial data line (SDA) coupled between the power supply and the battery backup unit, and a controller. A first monitor line is coupled between the controller and the 12C serial clock line, and a second monitor line is coupled between the controller and the 12C serial data line. The controller is configured to monitor a digital communication transmitted on the 12C serial clock and data lines between the power supply and the battery backup unit, interpret a message included in the monitored digital communication, and perform a control function according to the interpreted message.

Methods of guaranteed reception and of processing of a digital signal in an avionics system comprise a plurality of computers, each computer comprising processing electronics and a software layer, which, on receipt of an event, carries out the following steps: at a first instant, sending to each of the other computers of a first signal (ACK) of reception of the event; at a second instant termed “TimeOut ACK”, if the electronic computer has not received one of the first signals emanating from one of the other computers, sending of a second failure signal (FAIL) to each of the other computers; at a third instant termed “TimeOut GARANTEED”, if a second failure signal has been received by the computer, absence of taking into account of the event by the computer and if no failure signal has been received by the computer, taking into account of the event by the data processing electronics of the computer.

Example implementations relate to memory mode categorization. An example memory mode categorization can include determining local and remote data bandwidths received at each of a first processor and a second processor for a data sample, comparing the local and the remote data bandwidths to a first threshold bandwidth and a second threshold bandwidth, respectively, creating a traffic pattern for the data sample based on the comparison, and categorizing the data sample as being a candidate for a particular memory mode based on the created traffic pattern.

A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor. The monitor obtains memory unit access information and process information of the computer system. The memory unit access information includes the number of access times of each memory unit of the memory. The process information includes information about a mapping relationship between a virtual address and a physical address of each memory units accessed by the current running process. After generating monitoring information, which includes the frequency at which the current running process accesses each memory unit, according to the memory unit access information and the process information, the monitor feeds the monitoring information back to the processor. Thus, the processor can perform memory management according to the monitoring information.

Systems, methods, circuits, devices and computer-readable mediums for configuring serial devices are disclosed. In some implementations, a device comprises: an input for receiving first and second requests from a serial bus; a decoder coupled to the input and configured to determine if either of the first and second requests is a configuration mode request; a controller coupled to the decoder and configured to: in response to a determination that the first request is a configuration mode request, program a configuration block with configuration data obtained from the serial bus and alter a device behavior according to the configuration data; and in response to a determination that the second request is not a configuration mode request, perform one or more actions on the device according to the second request.

An apparatus, system, and method are provided for routing multiple diagnostic pathways. A protocol data unit (PDU) router may receive a diagnostic response. The PDU router may identify a diagnostic request corresponding to the diagnostic response, based on a comparison of a first PDU identifier associated with the diagnostic request and a second PDU identifier associated with the diagnostic response. The identify a routing path between the diagnostic target and a diagnostic client associated with the diagnostic request, based on the first PDU identifier and the second PDU identifier. The PDU router may route the diagnostic response to the diagnostic client, based on the routing path. The routing path may overlap at least a portion of a second routing path between the diagnostic target and a second diagnostic client.

A method includes establishing a power link between a power source and a computing device using a cable assembly, the cable assembly including at least one indicator, monitoring a status of the power link at the computing device, determining if the status of the power link includes establishing a communication link, and upon determining the status of the power link includes establishing the communication link determining a direction of data flow along the cable assembly associated with the communication link, and generating a signal using the at least one indicator, the signal indicating the direction of data flow along the cable assembly.

Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.

Embodiments provide apparatuses and systems in which slave power sequencers share a command bus and power sequence respective power groups through power sequence states of a power sequencing protocol in response to commands on the command bus. In some examples, a system may include a master power sequencer to output onto a command bus a command to perform a power sequencing protocol for transitioning the system from a first power state to a second power state, and a plurality of slave power sequencers sharing the command bus, each slave power sequencer to power sequence a respective power group to a next power sequence state in response to the command. Other examples are described and claimed.