The disclosure describes techniques that enable detection of memory leaks of software executing on devices within a computer network. An example network device includes memory and processing circuitry. The processing circuitry monitors a usage of the memory by a software component operating within the network device. The processing circuitry periodically determines a memory growth pattern score for the software component based on the usage of the memory. The processing circuitry also predicts whether the user-level process is experiencing a memory leak based on the memory growth pattern score. The processing circuitry applies confirmation criteria to current memory usage of the software component to confirm that the software component is experiencing the memory leak. When the software component is experiencing the memory leak, the processing circuitry generates an alert.

A method of operating a controller includes randomly transmitting a first command to a non-volatile memory device upon a read request from a host; receiving first read data corresponding to the first command from the non-volatile memory device; determining whether the number of first error bits of the first read data is greater than a first reference value; determining whether the number of first error bits is greater than a second reference value, when the number of first error bits is not greater than the first reference value; storing a target wordline in a health buffer, when the number of first error bits is greater than the second reference value; periodically transmitting a second command to the non-volatile memory device; and receiving second read data corresponding to the second command from the non-volatile memory device.

A method by one or more electronic devices to provision an infrastructure for a machine learning application in a multi-tenant on-demand serving infrastructure. The method includes storing a plurality of templates, wherein each of the plurality of templates indicates a scoring interface, a web server, a definition of a continuous integration pipeline, and a definition of a continuous deployment pipeline, receiving a request to provision the infrastructure for the machine learning application using a specified template from the plurality of templates, and provisioning the infrastructure for the machine learning application using the specified template to create a version control system repository, a continuous integration pipeline, and a continuous deployment pipeline.

Certain embodiments disclosed herein provide application-specific launch optimization. Aspects of the present disclosure include one or more cost functions for each application, where each cost function corresponds to a likelihood that a particular application should be placed into a particular pre-activation state. For each of the inactive applications, a respective one of the pre-activation states is selected based on comparing cost values obtained by evaluating the cost functions. Each of the inactive applications can be moved to or maintained in the respectively-selected pre-activation state to more efficiently provide an expedited application launch experience for a user.

The invention discloses a data structure-aware prefetching method and device on a graphics processing unit. The method comprises the steps of acquiring information for a memory access request in which a monitoring processor checks a graph data structure and read data, using a data structure access mode defined by a breadth first search and graph data structure information to generate four corresponding vector prefetching requests and store into a prefetching request queue. The device comprises a data prefetching unit distributed into each processing unit, each data prefetching unit is respectively connected with an memory access monitor, a response FIFO and a primary cache of a load/store unit, and comprises an address space classifier, a runtime information table, prefetching request generation units and the prefetching request queue. According to the present invention, data required by graph traversal can be prefetched more accurately and efficiently using the breadth first search, thereby improving the performance of GPU to solve a graph computation problem.

A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.

A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

A method includes obtaining a first memory log, where the first memory log includes log information of a plurality of garbage collections, and log information of each garbage collection includes a garbage collection time, and includes at least one of a downtime, memory usage after garbage collection, and memory usage before garbage collection, obtaining, based on log information in a first detection time window, first statistical information corresponding to the first detection time window, and determining, based on the first statistical information corresponding to the first detection time window, an anomaly degree corresponding to the log information in the first detection time window.

A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.