The Dynamically Determined Difference Regions Apparatuses, Methods and Systems (DDDR) transforms backup configuration request, backup data read response inputs via DDDR components into backup configuration response, changed blocks update request outputs. A write command for a data block to write to a data volume is detected. A data volume address of the data block is determined. A superset range associated with the data volume address is determined. Upon determining that the written-to flag of the superset range is set: extend a previously established written-to subset range within the superset range to include the data volume address when it is determined that the data volume address is not within the previously established written-to subset range. Upon determining that the written-to flag is not set: set the written-to flag and establish a new written-to subset range within the superset range that includes the data volume address. Execute the write command.

Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

The Dynamically Determined Difference Regions Apparatuses, Methods and Systems (DDDR) transforms backup configuration request, backup data read response inputs via DDDR components into backup configuration response, changed blocks update request outputs. A write command for a data block to write to a data volume is detected. A data volume address of the data block is determined. A superset range associated with the data volume address is determined. Upon determining that the written-to flag of the superset range is set: extend a previously established written-to subset range within the superset range to include the data volume address when it is determined that the data volume address is not within the previously established written-to subset range. Upon determining that the written-to flag is not set: set the written-to flag and establish a new written-to subset range within the superset range that includes the data volume address. Execute the write command.

In accordance with embodiments of the present disclosure, a compiler can compile source code to produce binary code that includes address shifting code inserted with memory operations. The address shifting code can shift addresses of memory operations that access locations in the kernel address space into address locations in the user space, thus avoiding speculative access into the kernel address space.

A method for simultaneously accessing a first DRAM device and a second DRAM device includes the steps of: in an active phase, generating a first signal at a first pad, wherein the first signal is provided for the first DRAM device to select a first memory bank group, and the first signal is not for the second DRAM device to select any memory bank group; and generating a second signal at the first pad, wherein the second signal is provided for the first DRAM device to select the first bank group, and the second signal and the first signal correspond to a same digital value.

In accordance with embodiments of the present disclosure, a binary translator can perform address shifting on the binary code of an executing application. Address shifting serves to shift the addresses of memory operations that can access locations in the kernel address space into address locations in the user space, thus avoiding speculative access into the kernel address space.

One embodiment provides a memory module for a computer system. The memory module can include a physical enclosure encompassing at least one multi-chip packaging (MCP) module and a memory interface for coupling the MCP module to a central processing unit (CPU) of the computer system. The MCP module can include a first memory chip, an extended-memory chip, and a memory controller for controlling access to the extended-memory chip.

A method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space. The service co-processor updates the service address space to create and maintain an independent copy of the main address space. The service co-processor receives a system dump request from the main processor, initiates a system dump, and responsive to initiating the system dump, ceases updating the service address space. The service co-processor, upon completion of the system dump, resets the service address space.

The present disclosure addresses the meltdown vulnerability resulting from speculative execution in a multi-core processing system. The operating system (OS) can be loaded for execution on one of several processing cores (OS core), while an application can be loaded for execution on another of the processing cores (application core). The OS core uses process page tables that map the entire kernel address space to physical memory. Conversely, the application core uses pages tables that map only a portion of the kernel address space to physical memory.

A data storage device includes a memory device and a memory controller. The memory controller is coupled to the memory device and configured to access the memory device and establish a physical to logical address mapping table and a logical address section table. The logical address section table records statuses of a plurality of logical address sections. Each status is utilized to indicate whether the physical to logical address mapping table records any logical address that belongs to the corresponding logical address section. The logical address section table includes a plurality of section bits in a plurality of dimensions. When the memory controller receives a write command to write data of a first predetermined logical address, the memory controller determines the section bit of each dimension corresponding to the first predetermined logical address, and accordingly sets a corresponding digital value for each section bit.