An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.

In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.

A computing device includes a host device and a storage device. The host device is configured to receive instruction information via a code bus based on a code address comprised in a code address map of particular address maps and receive data via a system bus that is separate from the code bus based on a data address included in a data address map. The storage device is configured to store target instruction information via the system bus and provide the target instruction information to the host device via the code bus in response to a request from the host device for an object code address included in the code address map and corresponding to the target instruction information.

Technologies disclosed herein provide cryptographic computing with cryptographically encoded pointers in multi-tenant environments. An example method comprises executing, by a trusted runtime, first instructions to generate a first address key for a private memory region in the memory and generate a first cryptographically encoded pointer to the private memory region in the memory. Generating the first cryptographically encoded pointer includes storing first context information associated with the private memory region in first bits of the first cryptographically encoded pointer and performing a cryptographic algorithm on a slice of a first linear address of the private memory region based, at least in part, on the first address key and a first tweak, the first tweak including the first context information. The method further includes permitting a first tenant in the multi-tenant environment to access the first address key and the first cryptographically encoded pointer to the private memory region.

Methods for controlled segregation of blocks of information encoded in the sequence of a biopolymer, such as nucleic acids and polypeptides, with rapid retrieval based on multiply addressing nanostructured data have been developed. In some embodiments, sequence controlled polymer memory objects include data-encoded biopolymers of any length or form encapsulated by natural or synthetic polymers and including one or more address tags. The sequence address labels are used to associate or select memory objects for sequencing read-out, enabling organization and access of distinct memory objects or subsets of memory objects using Boolean logic. In some embodiments, a memory object is a single-stranded nucleic acid scaffold strand encoding bit stream information that is folded into a nucleic acid nanostructure of arbitrary geometry, including one or more sequence address labels. Methods for controlled degradation of biopolymer-encoded blocks of information in the memory objects are also developed.

A memory controller includes a mapping data control unit configured to interrupt the generation of the additional mapping data, when during generation of additional mapping data, an operation for an address identical to a logical block address in the additional mapping data is performed, and to generate dummy mapping data. The additional mapping data may include mapping information indicating a mapping relationship between a logical block address and a physical block address.

To improve data throughput and data transfer rate, a contiguous block of host memory can be allocated for data transfers between the host system and an integrated circuit device such as a peripheral component. By using a contiguous block of memory that acts as a circular buffer, the memory address field of memory descriptors can be eliminated because the host system only need to inform the data movement engine of the length of each data transfer. The data movement engine can maintain pointers to keep track of the memory address in the host memory to read from and write to. After each data transfer, the relevant pointer can be incremented by a value corresponding to the length indicated in the memory descriptor for the transfer. As such, it is not necessary for the host system to provide the data movement engine with the memory address of each transfer.

one embodiment of a memory stores information, including address bits, on DNA strands and provides access using a pipeline of tubes, where each tube selectively transfers half of the strands to the next tube based on probing of associated address bits. Transfers are controlled by logic relating to the state of the tubes: The pipeline may be initialized to start at a high-order target address, providing random access without enzymes, synthesizing probe molecules or PCR at access time. Thereafter, a processing unit gets fast access to sequentially addressed strands each cycle, for applications like executing machine language instructions or reading blocks of data from a file. Another embodiment with a compare unit allows low-order random access. Provided that addresses are encoded using single-stranded regions of DNA where probe molecules may hybridize, other information may use any DNA encoding. Electronic/electrochemical (electrowetting, nanopore, etc.) embodiments as well as biochemical embodiments are possible.

A method of labeling logic number units in a storage system results in the use of the same label for related LUNs in different storage arrays. A first storage array includes a first source logical unit number LUN, the second storage array includes a first target LUN, and the first source LUN and the first target LUN are a pair of active-active LUNs. The first storage array sends an assignable-address set of selectable labels for the first source LUN to the address assignment apparatus. The second storage array sends an assignable-address set of selectable labels for the first target LUN to the address assignment apparatus. The address assignment apparatus selects a label that is in both assignable-address sets of the first source LUN and first target LUN, and assign that selected label to both LUNs. Thereafter, the address assignment apparatus sends the selected label to the first storage array and the second storage array for identifying both the first source LUN and the first target LUN.

Memory allocation techniques may provide improved security and performance. A method may comprise mapping a block of memory, dividing the block of memory into a plurality of heaps, dividing each heap into a plurality of sub-heaps, wherein each sub-heap is associated with one thread of software executing in the computer system, dividing each sub-heap into a plurality of bags, wherein each bag is associated with one size class of objects, creating an allocation buffer and a deallocation buffer for each bag, storing a plurality of objects in at least some of the bags, wherein each object is stored in a bag having size class corresponding to a size of the object, storing in the allocation buffer of each bag information relating to available objects stored in that bag, and storing in the deallocation buffer of each bag information relating to freed objects that were stored in that bag.