Patent classifications
G06F13/122
I/O co-processor coupled hybrid computing device
An apparatus and method provide power to perform functions on a computing device. In one example, the apparatus contains multiple processors that may operate at different power levels to consume different amounts of power. Also, any of the multiple processors may perform different functions. For example, one processor may be a low power processor that may control or operate at least one peripheral device to perform a low capacity function. Control may also switch from the low power processor to a high capacity processor. In one example, the high capacity processor controls the low power processor and further controls the at least one peripheral device through the lower power processor.
Multi-device asynchronous timing exchange for redundant clock synchronization
The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.
INPUT/OUTPUT FILTER UNIT FOR GRAPHICS PROCESSING UNIT
Input/output filter units for use in a graphics processing unit include a first buffer configured to store data received from, and output to, a first component of the graphics processing unit; a second buffer configured to store data received from, and output to, a second component of the graphics processing unit; a weight buffer configured to store filter weights; a filter bank configurable to perform any of a plurality of types of filtering on a set of input data, the plurality of types of filtering comprising one or more texture filtering types and one or more pixel filtering types; and control logic configured to cause the filter bank to: (i) perform one of the plurality of types of filtering on a set of data stored in one of the first and second buffers using a set of weights stored, and (ii) store the results of the filtering in one of the first and second buffers.
TEMPERATURE CONTROL DEVICE, INFORMATION PROCESSING APPARATUS, AND TEMPERATURE CONTROL METHOD
A temperature control device that is mounted on an information processing apparatus together with a temperature sensor, a fan, and a plurality of coupling parts that enable coupling of an expansion device, and that controls a temperature of the information processing apparatus, the temperature control device includes: a memory; and a processor coupled to the memory and configured to: hold, in the memory, a profile that indicates a relationship between a temperature of the information processing apparatus and rotational speed of the fan for each position of the coupling part to which the expansion device is coupled; receive, via a basic input and output program that operates exclusively with respect to an operating system, a profile for new expansion device received by the operating system when a driver for controlling a new expansion device newly mounted in the coupling part is installed in the information processing apparatus.
Communication system
The in-vehicle network includes a plurality of slave devices and a master device that communicates with the plurality of slave devices. The plurality of slave devices generates slave unique information as random information upon setting ID, and transmits the generated slave unique information. When all the slave unique information received from the plurality of slave devices are different from each other, the master device sets the ID based on each slave unique information. When the slave unique information received from the plurality of slave devices matches, the master device transmits a regeneration command to regenerate the slave unique information. Upon receiving the regeneration command, the slave device regenerates the slave unique information.
Remote input/output system
A remote I/O system includes an information network control module, I/O interface modules, and a remote I/O module. The information network control module includes a common memory and a second control IC. The second control IC includes a variation detecting circuit that includes a data latch buffer that stores read data from an information network; and a variation detection memory that stores data previously read from the information network. The variation detecting circuit compares data stored in the data latch buffer with data stored in the variation detection memory, to detect a variation in the data. The second control IC transmits, to the I/O interface module, by cyclic scan transmission, data from one of the scan memory areas corresponding to the data having the variation detected by the variation detecting circuit.
Enabling peripheral device messaging via application portals in processor-based devices
Enabling peripheral device messaging via application portals in processor-based devices is disclosed herein. In one embodiment, a processor-based device comprises a processing element (PE) including an application portal configured to logically operate as a message store, and that is exposed as an application portal address within an address space visible to a peripheral device that is communicatively coupled to the processor-based device. Upon receiving a message directed to the application portal address from the peripheral device, an application portal control circuit enqueues the message in the application portal. In some embodiments, the PE may further provide a dequeue instruction that may be executed as part of the application, and that results in a top element of the application portal being dequeued and transmitted to the application. Some embodiments may provide further mechanisms for sending success and/or failure notifications, and/or for informing the application that the message has been enqueued.
Data processing system with adjustable speed of processor and operating method thereof
A data processing system includes a controller configured to control data input/output for a memory according to a request of a host. The controller may include a buffer memory including a plurality of buffers configured to store data transmitted from the memory, a processor group including a plurality of cores respectively connected to the plurality of buffers, each core configured to read respective data from its respective buffer and perform computation using the read data, and a speed control component configured to adjust an operating speed of the processor group based on an amount of unread data of each buffer corresponding to each of the plurality of cores.
Wiring aggregation apparatus, wiring aggregation system, and contact information transfer method
A wiring aggregation apparatus includes at least one subunit. The subunit includes: an input/output module to output, to a control module, a first serial signal obtained by performing parallel-serial conversion on plural pieces of contact information collected from devices, and to output, to a corresponding device, each of plural pieces of contact information obtained by performing serial-parallel conversion on a second serial signal acquired from the control module; and the control module to generate a transmit frame by arranging the first serial signal acquired from the input/output module at a defined frame position, to transmit the generated transmit frame to another wiring aggregation apparatus, to extract the second serial signal arranged at a defined frame position from a receive frame acquired from the another wiring aggregation apparatus, and to output the extracted second serial signal to the corresponding input/output module.
Asynchronous timing exchange for redundant clock synchronization
The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.