A circuit system includes a processing integrated circuit die comprising a first die-to-die interface circuit and a memory interface circuit. The circuit system also includes a second integrated circuit die comprising a second die-to-die interface circuit and a compute circuit that performs computations for the processing integrated circuit die. The first and the second die-to-die interface circuits are coupled together. The compute circuit is coupled to exchange information with the memory interface circuit through the first and the second die-to-die interface circuits.

A wake-up control method for a Body Control Module (BCM) includes: step S1 writing IDs and wake-up level information of all Micro Controller Unit (MCU) pins serving as an external wake-up source to a retention RAM; step S2, setting a wake-up detection timer, and triggering a system to enter a low power consumption mode; step S3, after a wake-up detection time set by the wake-up detection timer expires, enabling power supply to all MCU pins, setting the corresponding MCU pin as an input pin according to the pin ID information written in step S1, and acquiring level information of the input pin; and step S4, comparing the level information of the input pin with the wake-up level information written in step S1, if they are consistent, writing the ID of the input pin that is to serve as a wake-up source to the retention RAM and triggering the system to enter a normal operating mode, and if they are inconsistent, disabling the power supply to the MCU pin. A wake-up control device for a BCM is further provided. The wake-up control method and the wake-up control device for a BCM reduce selection requirements for MCU chips, and provide more flexible hardware pin allocation and design for a wake-up source.

A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

A system, method, and apparatus are provided for handling communications with external communication channel hardware devices by a processor executing event-based programming code to interface a plurality of virtual machines with the external communication channel hardware devices by providing the processor with an event latch for storing hardware events received from the external communication channel hardware devices, with a timer circuit that generates a sequence of timer interrupt signals, and with a masking circuit that masks the hardware events stored in the event latch with an event mask in response to each timer interrupt signal, where each event mask is associated with a different virtual machine running on the processor such that each virtual machine is allowed to communicate only on a masked subset of the hardware events specified by the event mask to ensure freedom from interference between the plurality of virtual machines when communicating with the external communication channel hardware devices.

Memory module, computing device, and methods of reading and writing data to the memory module are disclosed. A memory module, comprises one or more dynamic random-access memories (DRAMs); and a processor configured to select a Central Processing Unit (CPU) or the processor to communicate with the one or more DRAMs via a memory interface.

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

An example system on a chip (SoC) includes a processor, a cache, and a main memory. The processor can receive a data packet from an electronic device via an interface device, the data packet comprising data for an offload processing task, where the data packet is in a standard link protocol format, the standard link protocol format comprising at least one of an offload protocol identification (ID) field, a tag field, a returned data length field, a flag field, a reserved field, a length field, or a data field. The processor can process the offload processing task to obtain result data. The processor can send the result data to the electronic device.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

Present invention disclose a hardware accelerator and a chip, and the hardware accelerator includes: an interface circuit and an accelerator core coupled to the interface circuit, where the interface circuit is configured to receive a first task request, perform decoding on the first task request to acquire identifier information, and configure, according to the identifier information, the first task request to be in an FIFO queue that matches the identifier information; a scheduling controller is configured to determine, from at least two channel groups, one or more target channel groups that have at least one to-be-processed second task request in an n.sup.th period, receive a time parameter that is fed back by the accelerator core and corresponding to the target channel group, and schedule the at least one second task request in the one or more target channel groups according to the time parameter and a weighted round robin algorithm.

A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.