A computing device including: more than two Universal Serial Bus (USB) ports configured to be connected respectively to more than two mobile devices simultaneously; at least one processor coupled to the USB ports; and a memory storing instructions configured to instruct the at least one processor to reprogram, through the more than two USB ports, the more than two mobile devices simultaneously.

According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the data to a node controller logic block, a central switch, or an optical interface based on one of a plurality of modes of operation of the multi-mode agent. The modes of operation may include a glueless mode where the PI interface is to route the data directly to the optical interface and bypass the node controller logic block and the central switch, a switched glueless mode where the PI interface is to route the data directly to the central switch for routing to the optical interface, and bypass the node controller logic block, and a glued mode where the PI interface is to route the data directly to the node controller logic block for routing to the central switch and further to the optical interface.

An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.

A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator.

Certain aspects direct a distributed Intelligent Platform Management Interface (D-IPMI) system. The system includes a computing device and a distributed management device. The distributed management device includes a first management device and at least one second management device physically separated from each other. A stack interface connects the first management device and the second management device to perform an internal communication between the first management device and the second management device. The first management device may be used to perform time critical functions related to the computing device, and the second management device may be used to perform non-critical functions. For example, the first management device may perform system power control of the computing device, monitor system components and obtaining system information of the computing device, and perform system communication with the computing device. The second management device may perform an external communication through the external interface.

A system and method for discovering fault conditions such as conflicts between applications and an operating system, driver, hardware, or a combination thereof, installed in mobile computing devices uses a mobile device running a diagnostic application. A list of applications that were launched or installed during a time period prior to an operational disruption is retrieved. A data table of combinations of incompatible programs and drivers is used to analyze the list of the applications that were launched or installed to create a list of potential fault-causing interactions due to software incompatibilities of software installed in the mobile computing device. A knowledge database is updated with data identifying at least one of the potential fault-causing interactions. Further disclosed is a computer program that identifies hardware-created or software-created problems and operational disruptions in mobile computing devices by collecting data on incompatibilities in particular mobile computing devices on the internet.

An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

A hardware architecture that may include: a host, a frontal engine, a parietal engine, a renderer engine, an occipital engine, a temporal engine, and a memory. The frontal engine may obtain a 5D tensor from the host and divide it into several groups of tensors. These groups of tensors may be sent or transmitted to the parietal engine, and the parietal engine may take the groups of tensors to further divide them into several tensors. The parietal engine may send these tensors to the renderer engine for execution and may send a partial amount of tensors to the occipital engine. The occipital engine may accumulate the partial amount of tensors and may execute them. The occipital engine may send the output feature as the final tensor to the temporal engine. The temporal engine may compress the final tensor before storing or saving it to the memory.

This system on chip comprises a plurality of master resources, a plurality of slave resources, a plurality of arbitration levels, each arbitration level being able to control the access of at least one master resource to at least one slave resource, each master resource being able to send requests to at least one slave resource according to a bandwidth associated with this slave resource and this master resource. The system is characterized by further comprising control means configured to control each bandwidth associated with each slave resource as a function of the capacity of this slave resource to process the requests originating from the master resource corresponding to this bandwidth.

Described herein are a processor and a method of operating the processor to simulate a many-core target machine. The processor includes a plurality of processing cores arranged in a predetermined manner and a global target clock counter (GTCC) configured to count a number of simulated clock cycles in the target machine. A global stall controller (GSC) configured to halt execution of all the processing cores based on a determination of at least one processing core being in a fault condition; and wherein the processor acquires a base clock per instruction (CPI) of a target machine, the CPI corresponding to an average number of clock cycles required by the target machine to execute a single instruction, translates an application of the target machine to a compact executable trace to be executed by the processor, and adjusts a speed of simulation by adjusting an update rate of the global target clock counter.