An optical image stabilization (OIS) circuit includes a first OIS circuit configured to operate as a serial peripheral interface (SPI) bus master with respect to a single sensor, read sensor data from the single sensor, and store the read sensor data, and configured to transmit a control code in a second SPI slave operation mode prior to a first SPI slave operation mode, and provide the sensor data in the first SPI slave operation mode, while operating as an SPI slave; and a second OIS circuit configured to operate as a SPI master with respect to the first OIS circuit, read the control code from the first OIS circuit, and store the control code in a first SPI master operation mode, and further configured to read and store the sensor data in a second SPI master operation mode subsequent to the first SPI master operation mode.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

A control device is used to adjust an output voltage of a voltage generator, and includes a master circuit, a slave circuit, and a power-scaling control circuit. The master circuit is coupled to a first bus. The slave circuit is coupled to a second bus. In a normal mode, the first and second buses are connected to each other via the power-scaling control circuit, the master circuit accesses the slave circuit via the first and second buses. In an adjustment mode, the power-scaling control circuit controls the master circuit to stop accessing the slave circuit, and the power-scaling control circuit adjusts the output voltage. When the master circuit sends a trigger signal, the power-scaling control circuit enters the adjustment mode. When the master circuit does not send the trigger signal, the power-scaling control circuit enters the normal mode.

A Time of Flight (TOF) system includes an incrementing circuit and a plurality of pixels. Each pixel includes a plurality of detectors configured to output respective detection signals responsive to detection of a plurality of photons incident thereon and a shared memory configured to store a respective count of the photons incident on each of the plurality of detectors. The incrementing circuit is configured to update the respective count for each of the plurality of detectors in the shared memory based on the respective detection signals.

Provided is a unit that causes transmission of smallest payload data to a communication interface to be in standby during a time period from a time, at which it is determined that a transmission time of smallest payload data exceeds a reference value during a control cycle, to a time at which the communication interface transmits the smallest payload data to be transmitted next after the most recent smallest payload data transmitted at the time.

The present description concerns a memory device (200) comprising: a memory circuit (201) implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit (205) receiving instructions from a processor (231), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit (203) of direct data transfer from or to said memory circuit (201), the transfer circuit (203) receiving instructions from the processor (231), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link (204) directly coupling said memory circuit (201) to the direct transfer circuit (203); and an arbitration circuit (309).

A data processing system includes a plurality of resources suitable for processing data, a host suitable for requesting at least one of the plurality of resources to process the data, a plurality of data paths suitable for transferring the data between the host and the plurality of resources, and an arbiter suitable for dividing the plurality of resources into a plurality of groups, allocating at least one first data path of the plurality of data paths to each of the groups, and rearranging the plurality of groups, based on their respective transmission statuses, by additionally allocating at least one second data path of the plurality of data paths to each of the groups or by moving at least one resource from one of the plurality of groups to another of the plurality of groups.

Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

A storage system and method for providing a dual-priority credit system are disclosed. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a plurality of credits for sending messages to the host; allocate a first portion of the plurality of credits for non-urgent messages; and allocate a second portion of the plurality of credits for urgent messages. Other embodiments are provided.