An integrated circuit (IC) device according to an example includes an interconnect bus to communicate with an external memory device, wherein the interconnect bus includes a plurality of different channels to be coupled directly to a first set of masters. The IC device includes a crossbar unit to be coupled to a second set of masters, wherein the crossbar unit is to monitor bandwidth usage at the plurality of different channels, and selectively route traffic between the second set of masters and the plurality of different channels based on the monitored bandwidth usage.

An integrated circuit (IC) device according to an example includes an interconnect bus to communicate with an external memory device, wherein the interconnect bus includes a plurality of different channels to be coupled directly to a first set of masters. The IC device includes a crossbar unit to be coupled to a second set of masters, wherein the crossbar unit is to monitor bandwidth usage at the plurality of different channels, and selectively route traffic between the second set of masters and the plurality of different channels based on the monitored bandwidth usage.

Ensuring the appropriate utilization of system resources using weighted workload based, time-independent scheduling, including: receiving an I/O request associated with an entity; determining whether an amount of system resources required to service the I/O request is greater than an amount of available system resources in a storage system; responsive to determining that the amount of system resources required to service the I/O request is greater than the amount of available system resources in the storage system: queueing the I/O request in an entity-specific queue for the entity; detecting that additional system resources in the storage system have become available; and issuing an I/O request from an entity-specific queue for an entity that has a highest priority, where a priority for each entity is determined based on the amount of I/O requests associated with the entity and a weighted proportion of resources designated for use by the entity.

Ensuring the appropriate utilization of system resources using weighted workload based, time-independent scheduling, including: receiving an I/O request associated with an entity; determining whether an amount of system resources required to service the I/O request is greater than an amount of available system resources in a storage system; responsive to determining that the amount of system resources required to service the I/O request is greater than the amount of available system resources in the storage system: queueing the I/O request in an entity-specific queue for the entity; detecting that additional system resources in the storage system have become available; and issuing an I/O request from an entity-specific queue for an entity that has a highest priority, where a priority for each entity is determined based on the amount of I/O requests associated with the entity and a weighted proportion of resources designated for use by the entity.

A memory control circuit includes an access storage unit configured to store access requests for a memory, a status management unit configured to, based on the access requests stored in the access storage unit, perform priority access type switching between two access types obtained by classifying the access requests, and an access selection unit configured to select and execute an access request stored in the storage unit. The access selection unit performs, if the priority access type switching is in progress and there is time for executing an access request of a priority access type before the priority access type switching, selecting the access request of the priority access type before the priority access type switching, and if the priority access type switching is not in progress, selecting an access request of the priority access type.

Priority reversing data traffic for latency sensitive peripherals, including receiving a connection notification and parameters of a peripheral; identifying, from the parameters, that an interface type associated with the peripheral is a bulk interface, the bulk interface associated with a first communication channel between the IHS and the peripheral and having a first latency; determining, based on the bulk interface type and a data traffic priority associated with the peripheral, that the data traffic associated with the peripheral is priority-inversed; in response to a communication request by an application executing on the IHS for communication with the peripheral, determining that the data traffic associated with the peripheral is priority-inversed, and in response, placing the data traffic in a queue associated with a second communication channel defined between the IHS and the peripheral, the second communication channel having a second latency, wherein the first latency is greater than the second latency.

Priority reversing data traffic for latency sensitive peripherals, including receiving a connection notification and parameters of a peripheral; identifying, from the parameters, that an interface type associated with the peripheral is a bulk interface, the bulk interface associated with a first communication channel between the IHS and the peripheral and having a first latency; determining, based on the bulk interface type and a data traffic priority associated with the peripheral, that the data traffic associated with the peripheral is priority-inversed; in response to a communication request by an application executing on the IHS for communication with the peripheral, determining that the data traffic associated with the peripheral is priority-inversed, and in response, placing the data traffic in a queue associated with a second communication channel defined between the IHS and the peripheral, the second communication channel having a second latency, wherein the first latency is greater than the second latency.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.

An integrated circuit (IC) device according to an example includes an interconnect bus to communicate with an external memory device, wherein the interconnect bus includes a plurality of different channels to be coupled directly to a first set of masters. The IC device includes a crossbar unit to be coupled to a second set of masters, wherein the crossbar unit is to monitor bandwidth usage at the plurality of different channels, and selectively route traffic between the second set of masters and the plurality of different channels based on the monitored bandwidth usage.

An integrated circuit (IC) device according to an example includes an interconnect bus to communicate with an external memory device, wherein the interconnect bus includes a plurality of different channels to be coupled directly to a first set of masters. The IC device includes a crossbar unit to be coupled to a second set of masters, wherein the crossbar unit is to monitor bandwidth usage at the plurality of different channels, and selectively route traffic between the second set of masters and the plurality of different channels based on the monitored bandwidth usage.