Systems and methods are disclosed to implement an endpoint command invocation system (“ECIS”). In some embodiments, ECIS can quickly dispatch a command to a large number of endpoint components, where the endpoint components are online. ECIS can receive an invocation of a command, which can include the command recipients. In some embodiments, ECIS determines that some of the command recipients are online, while some of the command recipients are offline. ECIS determines connections to the online command recipients based on a connection map, which is updated whenever an endpoint component opens a connection to ask for a command. ECIS can deliver the command to the online command recipients using the connections. ECIS can also deliver the command to dispatch queues corresponding to the offline command recipients, where the dispatch queues store the command as a pending command that can be delivered to their respective command recipients whenever they come online.

Systems and methods are disclosed to implement an endpoint command invocation system (“ECIS”). In some embodiments, ECIS can quickly dispatch a command to a large number of endpoint components, where the endpoint components are online. ECIS can receive an invocation of a command, which can include the command recipients. In some embodiments, ECIS determines that some of the command recipients are online, while some of the command recipients are offline. ECIS determines connections to the online command recipients based on a connection map, which is updated whenever an endpoint component opens a connection to ask for a command. ECIS can deliver the command to the online command recipients using the connections. ECIS can also deliver the command to dispatch queues corresponding to the offline command recipients, where the dispatch queues store the command as a pending command that can be delivered to their respective command recipients whenever they come online.

A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.

A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.

A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response performs at least one pre-work action that reduces a latency of the decoded memory command of the second type.

Methods and apparatus monitor memory access activities of non-real-time processing engines to determine time intervals when the memory access activities are low. When such time intervals are found, the methods and apparatus perform burst memory access control for real-time processing engines by bursting data from a memory to a burst memory buffer, or from the burst memory buffer to the memory, to allow fast data access by the real-time processing engines.

Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein.

Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein.

A method includes in response to receiving an I/O request for the storage system, determining information associated with the I/O request; generating a timestamp associated with the I/O request; and recording the information and the timestamp to reproduce an operation associated with the I/O request. A method comprises: in response to a request for reproducing an I/O operation of the storage system, obtaining information associated with at least one I/O request for the storage system, the information being recorded in response to reception of the at least one I/O request; obtaining at least one timestamp corresponding to the at least one I/O request; and reproducing the operation of the at least one I/O request on the storage system based on the information and the at least one timestamp.

According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.