A problem to be solved by the present invention is, in a computer system, to reduce processing delay from wait times which occur in timer access. According to the present invention, using either a CPU core (hereinafter “processing core”) other than a CPU core which executes an application, or a DMA device, a latest timer value is always transferred from a timer device to a primary storage device. The processing core reads the transferred value upon the primary storage device instead of accessing a register of the timer device, thereby avoiding a wait which occurs when directly reading the timer value of the timer device. The transfer of the value is carried out asynchronously from the processing of the processing core, thus obviating the need for the processing core to wait for the completion of the transfer. Accordingly, it is also unnecessary for the processing core to process an interrupt or a notification from another CPU core or the DMA device.

In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processor to manage events. A processor includes a first performance counter to increment upon occurrence of a first type of event in the processor and a second performance counter to increment upon occurrence of a second type of event in the processor. The processor is to reset the second performance counter in response to the first performance counter reaching a first limit.

In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processor to manage events. A processor includes a first performance counter to increment upon occurrence of a first type of event in the processor and a second performance counter to increment upon occurrence of a second type of event in the processor. The processor is to reset the second performance counter in response to the first performance counter reaching a first limit.

In some embodiments, a system is provided for communicating USB information via an extension medium. The system comprises an upstream facing port device (UFP device) and a downstream facing port device (DFP device). The UFP device and the DFP device are communicatively coupled via a non-USB extension medium, and allow a host device communicatively coupled to the UFP device and a USB device communicatively coupled to the DFP device to communicate via USB-compliant techniques. In some embodiments, the DFP device generates synthetic request packets to request additional data packets from the USB device compared to those requested by the host device. In some embodiments, the DFP device is configured to store a request packet in a packet queue if the request packet is received from the UFP device while the DFP device is busy receiving a response to a previous synthetic request packet from the USB device.

In some embodiments, a system is provided for communicating USB information via an extension medium. The system comprises an upstream facing port device (UFP device) and a downstream facing port device (DFP device). The UFP device and the DFP device are communicatively coupled via a non-USB extension medium, and allow a host device communicatively coupled to the UFP device and a USB device communicatively coupled to the DFP device to communicate via USB-compliant techniques. In some embodiments, the DFP device generates synthetic request packets to request additional data packets from the USB device compared to those requested by the host device. In some embodiments, the DFP device is configured to store a request packet in a packet queue if the request packet is received from the UFP device while the DFP device is busy receiving a response to a previous synthetic request packet from the USB device.

The disclosed embodiments provide a mechanism to support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

The disclosed embodiments provide a mechanism to support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

Disclosed is a hardware acceleration based automatic read control system and method for a serial peripheral interface (SPI). The automatic read control system includes an SPI module, an advanced peripheral bus (APB) module, an interrupt generation module, a direct memory access (DMA) controller, a state schedule control module, a register group module, a count signal generation module, a transmitted data buffer and a received data buffer; the state schedule control module, the register group module and the count signal generation module form a state machine system; and the state schedule control module controls automatic timed batch read of sensor data of the SPI according to configuration information of the register group module and counting and timing information of the count signal generation module.