This application discloses a method and an apparatus, an electronic device, and a computer-readable storage medium for implementing data transmission. The method is executed by an electronic device providing a computing service, and is applied to execution of data transmission between two buses of different types, wherein one of the two buses is associated with an FPGA instance among multiple FPGA instances run by the computing service and the other of the two buses corresponds to an external device to the electronic device, the method including: obtaining an access instruction from an initiator through a first bus of the two buses for data read/write in a target, wherein the initiator and the target are associated with the first bus and a second bus of the two buses, and comprise one and the other of the FPGA instance and the external device, respectively; buffering the access instruction into an instruction storage area corresponding to the access instruction; and transmitting the access instruction buffered in the instruction storage area to the target continuously, and suspending transmission of the access instruction to the target once a flow control is imposed.

A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.

The present disclosure provides a hot-plugging control method, device, and retimer. The hot-plugging control method includes: receiving data from a pluggable device through a second end, sending the data to an RC through a first end; sending a detection signal to the second end to detect the connection status between the pluggable device and the second end; and stopping sending the data to the RC, and sending the first control signal to the RC, when it is detected that the pluggable device is hot-unplugged from the second end, so that the RC handles the abnormal state of the data not being sent according to the first control signal. The hot-plugging control method provided by the present disclosure does not require presence signals to implement hot-plugging of a pluggable device, and thus can avoid the problem that the device cannot implement hot-plugging without presence signals.

Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.

A discrete three-dimensional (3-D) processor a plurality of storage-processing units (SPU's), each of which comprises a non-memory circuit and more than one 3-D memory (3D-M) array. The preferred 3-D processor further comprises communicatively coupled first and second dice. The first die comprises the 3D-M arrays and the in-die peripheral-circuit components thereof; whereas, the second die comprises the non-memory circuits and off-die peripheral-circuit components of the 3D-M arrays.

Capacitive coupling may enable more tightly synchronized operation of components in a multi-domain distributed driver that provides slope-controlled switching of differential signal lines. One illustrative distributed driver includes: a first set of transistors each coupled to drive a first bus line; a first set of delay elements configured to enable and disable the first set of transistors sequentially; a second set of transistors each coupled to drive a second bus line; a second set of delay elements configured to enable and disable the second set of transistors sequentially; and at least one capacitance coupling a first node in the first set of delay elements to a corresponding second node in the second set of delay elements to synchronize signal transitions at the first and second nodes.

Provided are a method and apparatus for multi-bus device fused access. The method includes: receiving, by a bus, an instruction for accessing a fused node of a device, which instruction containing a matching word, an initial address, and an offset; performing matching according to the matching word and activating a fused drive; acquiring, by the fused drive, the initial address and the offset from the instruction on the bus respectively; computing an address of a first bus of the device according to the initial address, and computing an address of a second bus of the device according to the initial address and the offset; and accessing the device according to the address of the first bus so as to acquire first information, and accessing the device according to the address of the second bus so as to acquire second information.

A technique capable of normally transmitting a LPM token from a transceiver to a USB device is provided. A semiconductor device includes: a controller including a first interface circuit in conformity with UTMI+ standards; a converting circuit including a second interface circuit in conformity with the UTMI+ standards and a third interface circuit in conformity with ULPI standards, the second interface circuit converting data transmitted from the first interface circuit and received, and the third interface circuit transmitting the converted data; a first circuit analyzing a packet output from the controller and identifying and holding a packet identifier contained in the packet; and a second circuit providing a transmission command, after which a data string containing the packet identifier indicating LPM bringing a USB device to a low power consumption state is added, if the first circuit determines that the packet identifier is the LPM.

Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.