Reconfigurable interconnection nodes and interface modules are provided. The reconfigurable interconnection node includes a circuit board with a processing unit executing instructions stored on memory to provide operating system software, at least one bus, and at least one bus connector. The reprogrammable interconnection node also includes at least one system interface module operably connected to the circuit board via the at least one bus, wherein the system interface module is configured to communicate with or exchange data with at least a first external system.

Methods and Systems are described for control at/of a network node. The network node can include a control module and first and second modules coupled to the control module. The first module can be configured to select first input/output (I/O) types of a field device coupled at an I/O interface of the network node. The second module can be configured to select a second I/O types of the field device. The first and second modules can be coupled to the I/O interface through a field device coupler.

The present disclosure provides a storage system including a first storage device (e.g., a main storage device) and one or more additional storage devices (e.g., sub storage devices). The first storage device includes a host interface for communicating with a host device and is directly connected to the host device. The additional storage devices may be directly connected to the first storage device and may communicate with the host device through the host interface included in the first storage device. The storage system thus has a total combined capacity of both the capacity of the first storage device and the capacity of the one or more additional storage devices. Further, the one or more additional storage devices may be added or removed to increase or decrease the total capacity of the storage system, and the one or more additional storage devices may not necessarily themselves include a host interface.

[Overview] [Problem to be Solved] To provide a communication device and a communication system that each enable transmission of a command and data of I3C in a protocol different from the I3C. [Solution] A communication device according to a first aspect of the present disclosure includes: an I3C device section that generates a command and data of I3C; and a communication device section that transmits the command and data of the I3C to another communication device via a bus by using a payload in a protocol different from the I3C.

A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.

A stand alone low cost writing pad includes a rechargeable battery, a low capacity memory, a low power processor, a first pair of connectors and supports audio, video and digital ink capturing functionalities. The writing pad may be detached from and re-attached to a stand alone base unit using the first pair of connectors. The base unit includes another rechargeable battery, high capacity memory, high power processor, and a second pair of connectors. The base unit receives captured audio and digital ink from the writing pad via the communication pathway and the high power processor runs voice recognition and optical character recognition software on received data to generate second data. The second data is displayed on the writing pad and/or stored in the high capacity memory for future use.

Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator.

An apparatus having a plurality of buffers, a first circuit and a second circuit is disclosed. The buffers are configured to store a plurality of frames to be transmitted in a plurality of respective lanes of a communication channel. The first circuit is configured to (i) generate a plurality of first groups from a first number of a plurality of samples, at least one of the first groups contains an initial portion of a given one of the samples, and (ii) generate a first of the frames by appending the first groups. The second circuit is configured to (i) receive a final portion of the given sample from the first circuit, (ii) generate a plurality of second groups from the final portion of the given sample and a second number of the samples and (iii) generate a second of the frames by appending the second groups.

Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

A network includes a management module with a first root complex, a first server with a first endpoint coupled to the first root complex, and a second server with a second root complex, a second endpoint coupled to the second root complex, a third endpoint coupled to the first root complex, and a bridge coupled to the second endpoint and to the third endpoint. A method includes discovering a PCIe host bridge adapter (PHBA) and a storage resource coupled to multiple storage extents in a PCIe domain, creating a first virtual function on the storage resource and sending a first identifier for the first virtual function to the PHBA. A network interface device includes a PCIe endpoint that is coupleable to a PCIe root complex, another PCIe endpoint that is coupleable to another PCIe root complex, and a bridge that couples the first PCIe endpoint with the second PCIe endpoint.