An electronic device includes a CPU, an acceleration module, and a memory. The acceleration module is communicatively connected with the CPU, and includes chips. The chip according to an embodiment includes a data bus, and a memory, a data receiver, a computing and processing unit, and a data transmitter connected to the data bus. The data receiver receives first data and header information from outside, writes the first data to a corresponding area of the memory through the data bus, and configures a corresponding computing and processing unit and/or data transmitter according to the header information. The computing and processing unit receives first task information, performs an operation processing according to the first task information and a configuration operation on the data transmitter. The data transmitter obtains second task information and second data, and outputs third data to outside based on at least part of the second data.

A memory device is configured to communicate with one or more external devices, the memory device including a configurable bit or a mode select pin for determining which one of two or more different communication protocols that the memory device uses to communicate with the one or more external devices, wherein the two or more different communications protocols include at least a Controller Area Network (CAN) protocol and a System Management Bus (SMBus) protocol.

A method and device are for recognizing an apparatuses and computer readable storage medium and program are provided. In an embodiment, the method includes reading a combined sequence table including candidate device information, candidate communication parameters and historical occurrence numbers of combinations of the candidate device information and the candidate communication parameters for each candidate device information; determining priority levels of the combinations according to the historical occurrence numbers; and determining a current combination according to the priority levels, sending a message to the apparatus to be recognized by using a candidate communication parameter in the current combination, and determining whether the current combination is the correct combination capable of establishing a communication with the apparatus to be recognized according to a feedback from the apparatus to be recognized. The recognition efficiency may be improved effectively and the recognition time may be shortened significantly through the method.

A method of improving synchronization over a secure digital (SD) bus between an SD host and an SD client device is described. The method includes writing to a client event register to interrupt the SD host for an SD extended command. The method also includes triggering the SD host to issue the SD extended command to the SD client device over the SD bus in response to the SD client device writing to the client event register.

Embodiments herein describe using software or firmware to manage the device capability list of a PCIe device. That is, rather than relying on pure hardware to advertise the capabilities of a PCIe device, the embodiments herein permit software or firmware executing on a processor in the PCIe device to manage read and write requests associated with discovering the capabilities of the device and configuring the device.

System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.

An information processing device includes a computer system and a dedicated device connected via a dedicated bus, wherein the computer system implements a monitoring unit via an operating system thereof. The monitoring unit includes a detection module configured to detect the blocked state of the dedicated bus, and a blocking release module activated upon detecting the blocked state of the dedicated bus and configured to perform a blocking release process for instructing the operating system to disconnect the dedicated device, for releasing the blocked state of the dedicated bus, for instructing the operating system to reset the dedicated device disconnected from the computer system, and for instructing the operating system to reconnect the dedicated device to the computer system after resetting the dedicated device.

In example implementations, an apparatus is provided. The apparatus includes an interface, a previous generation carrier connected to the interface, a controller communicatively coupled to the interface, and a basic input/output system (BIOS). The previous generation carrier includes a current generation memory card. The controller is to detect the previous generation carrier. The BIOS is to set the interface to operate at a speed associated with the previous generation carrier in response to detection of the previous generation carrier.

Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.

The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.