The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T.sub.1 . . . T.sub.4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T.sub.1 . . . T.sub.4 at least one of the four signals has an edge to enable clock recovery at the second IC.

A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.

The present application discloses a gateway device for managing multiple electronic tags. The gateway device includes a network modem configured to receive updated data for multiple electronic tags. Additionally, the gateway device includes a communication chip configured to transmit individual updated data for each individual electronic tag one by one to the corresponding individual electronic tag of the multiple electronic tags. Moreover, the gateway device includes a microcontroller coupled with the network modem and the communication chip to control receiving the updated data for the multiple electronic tags from the network modem and transmitting multiple individual updated data respectively to the multiple electronic tags.

A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

The present invention relates to a communication chipset, a communication device and a protocol offload method for automatic address allocation, and the communication chipset includes: a plurality of registers for storing address setting modes and IP addresses; a controller-interface for setting the address setting mode on the basis of a data received from a controller controlling an offload device through execution of a program; a network-interface for transmitting and receiving a network packet; and an IP address creation control module for automatically setting an IP address of the plurality of registers using the received network packet according to the set address setting mode.

A bus control circuit configured to transfer access commands for performing exclusive access between a first bus specification and a second bus specification by converting from a first exclusive access command applying to the first bus specification which deals with exclusive access, into a second exclusive access command of the second bus specification which doesn't deal with the exclusive access. The circuit includes an exclusive access command conversion circuit for receiving the first exclusive access command, converting the first exclusive access command into the second exclusive access command, and outputting the second exclusive access command; an exclusive access command generation circuit for receiving the second exclusive access command and generate the first exclusive access command; an exclusive access response issuing circuit for issuing exclusive access response information for the second exclusive access command; and an exclusive access response receiving circuit for receiving exclusive access response information for the second exclusive access command.

A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

A speech recognition device includes a voice collection module configured to collect voices; a voice denoising module electrically connected to the voice collection module and configured to denoise the collected voice; a voice recognition module electrically connected to the voice denoising module and configured to recognize voices denoised by the voice denoising module and converted the denoised voices into control instructions; an interface conversion module electrically connected to the voice recognition module and configured to convert the control instructions into digital signals; and a parallel port interface electrically connected to the interface conversion module and configured to be inserted into an electronic device so that the digital signals can be transmitted to the electronic device via the parallel port interface. The present invention provides a new speech recognition device and system to fast response to simple operation instructions without cloud recognition operation.

A data processing system comprising a decompression circuit, configured to decompress compressed data to generate decompressed data. The decompression circuit comprises: a request transmitting terminal, configured to transmit a data receiving request indicating the decompressed data to be received; a valid information transmitting terminal, configured to transmit valid information indicating which part of the decompressed data is valid; and a data transmitting terminal, configured to transmit the decompressed data. An image processing circuit corresponds to the decompression circuit is also disclosed.