Patent classifications
G06F15/167
System and method for providing additional functionality to existing software in an integrated manner
An improved system and method are disclosed for improving functionality in software applications. In one example, the method includes a computing entity having a network interface, a processor, and a memory configured to store a plurality of instructions. The instructions include instructions for a superblock application having instructions for a function block included therein. The function block is configured to provide functions that are accessible to the superblock application via an application programming interface (API). The functions are provided within the superblock application itself and are accessible within the superblock application without switching context to another application on the computing entity.
ELECTRONIC DEVICE AND PROCESSING METHOD
An electronic device includes a first processing unit and a second processing unit, a first memory unit correspondingly set for the first processing unit and configured for data access by the first processing unit, and a second memory unit correspondingly set for the second processing unit and configured for data access by the second processing unit. The first processing unit occupies at least part of storage space of the second memory unit when a first criteria is met, and/or the second processing unit occupies at least part of storage space of the first memory unit when a second criteria is met.
DEVICE AND METHOD FOR SHARED MEMORY PROCESSING AND NON-TRANSITORY COMPUTER STORAGE MEDIUM
A device for shared memory processing is provided in implementations of the disclosure. The device for shared memory processing includes a set of shared memory units, a set of processing units, and a set of global clock synchronizers. Each shared memory unit corresponds to one global clock synchronizer and is coupled with K processing units via the corresponding global clock synchronizer, and the coupled K processing units perform conflict-free memory access to the shared memory unit during one instruction cycle of the corresponding global clock synchronizer. One instruction cycle of each global clock synchronizer includes N clocks, K is less than or equal to N, and K and N are integers greater than zero. A method for shared memory processing and a non-transitory computer storage medium are also provided.
AUTHORING MANAGEMENT METHOD BASED ON RELATION OF ELECTRONIC DOCUMENTS AND AUTHORING MANAGEMENT SYSTEM
An authoring management method includes: a content designated section setting step of setting a designated section in an electronic document; an RD authored content collection step of collecting first RD content and corresponding first mark-up information as first RD authored content; an identification information creation step of creating the identification information of the first RD authored content; a correlation collection step of collecting a correlation between the first RD authored content and another piece of RD authored content; a relation attribute collection step of collecting a relation attribute regarding the nature of a change between the first authored RD content and the other piece of authored RD content; an RD creation step of creating a first RD; and a storage step of storing the first RD in an RDDB and also storing the electronic document in an electronic document DB.
ACCESS CONTROL CONFIGURATIONS FOR INTER-PROCESSOR COMMUNICATIONS
Methods, systems, and devices for access control configurations for inter-processor communications are described to support reconfiguration of a dynamic access control configuration at a device. For example, additional configuration fields may be added to existing access control rules of the device, where these additional fields may be configured by a processor sending information to a receiving processor, via a shared memory resource or region of the device. The additional fields may include a read-only value which may specify a processor which has exclusive write permission for a memory region of the share memory. This value may indicate the sending processor of the memory region, and the value may be set by access control hardware when the additional field is changed. Other processors of the device may be prevented from writing to the memory region.
A Network Computer with External Memory
A computer comprising a plurality of processor devices connected in a ring, wherein each of the processor devices is connected to each of two neighbouring ones of the processor devices by a respective physical inter-processor link. Each of a set of external memory device stores a local portion of the externally stored dataset. Each processor device executes instructions to: determine that a synchronisation point has been reached by the plurality of processor devices; responsive to the determination, access from its connected external memory device its local portion of the externally stored dataset stored; record a copy of its local portion of the externally stored dataset in its local memory; transmit its local portion of the externally stored dataset to at least one of its connected neighbouring processing devices; and receive an incoming portion of the externally stored dataset from at least one of its connected neighbouring processing devices.
Systems and methods for efficient data buffering
In one embodiment, one or more control units may store a position tracker associated with a first window of memory blocks and allow a first processing unit to write data within the first window. The control units may receive, from a second processing unit, a request for reading data with a memory-reading address, compare the memory-reading address to a first starting address of the first window, and prevent the second processing unit from reading the data when the memory-reading address is greater than or equal to the first starting address of the first window. The control units may store, when the data writing process is complete, an updated position tracker of a second window of memory blocks and allow the second processing unit to read the data based on a determination that the memory-reading address is less than a second starting address of the second window.
Optimizing memory bandwidth in spatial architectures
A technique to facilitate efficient, parallelized execution of a program using a multiprocessor system having two or more processors includes detecting and, optionally, minimizing broadcast data communication between a shared memory and two or more processors. To this end, the broadcast space of a data structure is generated as an intersection of the reuse space of the data structure and the placement space of a statement accessing the data structure. A non-empty broadcast space implies broadcast data communication that can be minimized by rescheduling the statement accessing the data structure.
WIND TURBINE CONTROL ARCHITECTURE
A wind turbine control architectures, including a turbine control portion which is configured to control at least one component of a wind turbine, and a turbine data storage portion which is configured to store a data storage container therein is provided. The turbine control portion and the turbine data storage portion communicate with each other via an inter-process communication.
CONTROL CIRCUIT, INFORMATION PROCESSING SYSTEM, AND CONTROL METHOD
In a control circuit, a request storage unit including a plurality of entries for storing an access request, to which a priority and attribute information are applied, stores the received access request, a priority update unit updates the priority of the access request based on the priority and the attribute information of the access request stored in the request storage unit, and a request selection unit selects and transmits the access request stored in the request storage unit based on the updated priority.