An electronic device and a power control method of an electronic device are provided. The electronic device may include: a communication circuit including a first circuit configured to perform first communication and a second circuit configured to perform second communication; a processor electrically connected to the communication circuit; and a memory electrically connected to the processor, wherein, the memory stores instructions that, when executed, cause the processor to perform operations comprising: controlling the first circuit to operate according to a first power control mode associated with the first communication, and controlling the second circuit to operate according to a second power control mode associated with the second communication when the first communication and the second communication are concurrently performed through the first circuit and the second circuit; identifying a first sleep period during which the first circuit operates in a sleep mode according to the first power control mode, and a second sleep period during which the second circuit operates in the sleep mode according to the second power control mode; and controlling the communication circuit to operate in a deep sleep mode in which the communication circuit operates with power that is less than or equal to a predetermined power in a period where the first sleep period and the second sleep period coincide.

Embodiments of the present disclosure relate to communication methods and devices for virtual base stations. For example, data is sequentially read and written between the hardware accelerator and the general purpose processor of the baseband processing unit at the baseband processing unit arranged with a plurality of virtual base stations, thereby achieving sharing of the traditional hardware accelerator among a plurality of virtual base stations without introducing virtualization layer or increasing hardware complexity.

A system includes a memory, an interface engine, and a master. The memory is configured to store data. The inference engine is configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data. The master is configured to interleave an address associated with memory access transaction for accessing the memory. The master is further configured to provide a content associated with the accessing to the inference engine.

A communication control device, includes a memory; and a processor coupled to the memory and the processor configured to: store, in the memory, instructions of standby processing in a specific processing order, when a network coupling is being established to perform communication, acquire a specific instructions, update, in the memory, the instructions of standby processing based on a type of the specific instructions, a type of the instructions of standby processing and a relationship specified by order in which the specific instructions are acquired, and after an establishment of the network coupling is completed, perform the instructions of standby processing in a specific processing order.

A communication control device, includes a memory; and a processor coupled to the memory and the processor configured to: store, in the memory, instructions of standby processing in a specific processing order, when a network coupling is being established to perform communication, acquire a specific instructions, update, in the memory, the instructions of standby processing based on a type of the specific instructions, a type of the instructions of standby processing and a relationship specified by order in which the specific instructions are acquired, and after an establishment of the network coupling is completed, perform the instructions of standby processing in a specific processing order.

A semiconductor integrated-circuit device comprises two processing subsystems, each comprising a respective processor, set of local peripherals, and bridge unit, all connected to a respective local bus. An electrical interconnect joins the respective bridge units. The first bridge unit comprises a task register, accessible over the first local bus, and can be configured to detect a write to the task register, and respond by sending an event signal over the interconnect to the second bridge unit. The second bridge unit can be configured to receive the event signal, and respond by sending an interrupt signal to the second processor.

A computer-readable medium may store machine-readable instructions for execution by a processor. There may be a connection between the processor and a virtual computer. The processor may establish a first data channel between the processor and the virtual computer based on the connection between the processor and the virtual computer. The connection may comprise a second data channel to transfer input/output (I/O) data between the processor and the virtual computer. The processor may receive an input signal from an I/O device coupled to the processor. The processor may provide an input message to the virtual computer via the first data channel, the input message based on the input signal.

A multiprocessor system including at least a first processor and a second processor, includes a storage unit that stores a first program executed by the first processor and a second program executed by the second processor, a memory unit that has a memory region used by the second processor, and a monitoring unit that is connected to the storage unit and the memory unit via a communication line, and, in a case where a program read from the storage unit is the second program, stores the read second program into the memory unit.

A multiprocessor system including at least a first processor and a second processor, includes a storage unit that stores a first program executed by the first processor and a second program executed by the second processor, a memory unit that has a memory region used by the second processor, and a monitoring unit that is connected to the storage unit and the memory unit via a communication line, and, in a case where a program read from the storage unit is the second program, stores the read second program into the memory unit.

A computer system includes a plurality of servers connected to each other via a communication line, each server including a memory and a processor, an OS program and a storage program. The storage program is executed by the processor, and one of the plurality of servers acts as a request source server while one of the other servers acts as a request destination server. When the request source server reads data from the request destination server, the processor of the request source server executes the storage program to transmit a data read request to the request destination server. The processor of the request destination server then executes a storage memory driver incorporated in the OS program to read the requested data from an own memory and transmit the read data to the request source server. The request source server then executes the storage program to acquire the data.