Patent classifications
G06F15/17
Computer system, processing method, and driver program
A computer system includes a plurality of servers connected to each other via a communication line, each server including a memory and a processor, an OS program and a storage program. The storage program is executed by the processor, and one of the plurality of servers acts as a request source server while one of the other servers acts as a request destination server. When the request source server reads data from the request destination server, the processor of the request source server executes the storage program to transmit a data read request to the request destination server. The processor of the request destination server then executes a storage memory driver incorporated in the OS program to read the requested data from an own memory and transmit the read data to the request source server. The request source server then executes the storage program to acquire the data.
High-performance input-output devices supporting scalable virtualization
Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.
User interface with expected response times of commands
A method for determining a performance trend of a software application based on performance indicators of the software application. The method receives corresponding access requests from the client computing machines from a user interface framework of the software application that includes at least one command for submitting corresponding operation requests, and estimates corresponding expected response times of the software application for serving the operation requests in response to the access requests. The expected response time of each of the operation requests is estimated according to a comparison of the operative conditions that correspond to the operation request with the performance trend. The method transmits corresponding performance artifacts that are based on the expected response times associated with the user interface framework, to the client computing machines that cause the client computing machines to provide corresponding warnings.
System, method and apparatus for inter-process communication
A system, apparatus and method for enabling a FIFO-like (first-in-first-out) communication between a plurality of executing processes that are distributed throughout a computing system. Embodiments exploit locality in the hierarchy of the cache memory and communication busses within the computing system to enable the passing of messages or streams of bytes with a low latency and high throughput. In addition, this allows for participating components to be very simple, or very sophisticated, but still benefit from the improved communications patterns.
System, method and apparatus for inter-process communication
A system, apparatus and method for enabling a FIFO-like (first-in-first-out) communication between a plurality of executing processes that are distributed throughout a computing system. Embodiments exploit locality in the hierarchy of the cache memory and communication busses within the computing system to enable the passing of messages or streams of bytes with a low latency and high throughput. In addition, this allows for participating components to be very simple, or very sophisticated, but still benefit from the improved communications patterns.
Circuit architecture mapping signals to functions for state machine execution
An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.
Circuit architecture mapping signals to functions for state machine execution
An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.
SYSTEMS & METHODS FOR MULTI PF EMULATION USING VFS IN SSD CONTROLLER
A Lightweight Bridge (LWB) is disclosed. The LWB may be a circuit. An endpoint of the LWB that may expose a plurality of Physical Functions (PFs) to a host. A root port of the LWB may connect to a device and determine the PFs and Virtual Functions (VFs) exposed by the device. An Application Layer-Endpoint (APP-EP) and an Application Layer-Root Port (APP-RP) may translate between the PFs exposed by the endpoint and the PFs/VFs exposed by the device. The APP-EP and the APP-RP may implement a mapping between the PFs exposed by the endpoint and the PFs/VFs exposed by the device.
On-chip communication system for neural network processors
The present disclosure provides an on-chip communication system for neural network processors, a processing device, and a method for operating on an on-chip communication system. The system can include a cluster manager configured to generate a global signal, and a plurality of tile units in a tile array coupled with the cluster manager, each including two connectors and a node connected between the two connectors.
COMMUNICATION SYSTEM AND COMMUNICATION CONTROL METHOD
Provided is a communication system including: a first communication bus available for communication of at least a first communication scheme; a second communication bus available for both communication of the first communication scheme and communication of a second communication scheme having a lower processing load than the first communication scheme; a plurality of first communication devices connected to both the first communication bus and the second communication bus; a plurality of second communication devices, connected to the second communication bus, which perform communication through the second communication scheme using the second communication bus; and a processor that detects an abnormality of the first communication bus, wherein each of the plurality of first communication devices performs communication through the first communication scheme using the first communication bus in a case where the abnormality of the first communication bus is not detected by the processor, and performs communication through the first communication scheme using the second communication bus in a case where the abnormality of the first communication bus is detected by the processor.