Provided efficiently and at low cost are: a package for core number ratios appropriate for all types of computers; and dies included in the package. This package includes at least one die provided with: at least one of a first core formed of a CPU core or a latency core and a second core formed of an accelerator core or a throughput core; an external interface; memory interfaces 24 to 26; and a die interface 23 which is connected to another die. The die includes a first type die and a second type die each including both the first core and the second core and the core number ratio between the first core and the second core in the first type die differs from that in the second type die. Moreover, the memory interfaces include an interface conforming to TCI. In addition, the memory interfaces further include an interface conforming to HBM.

Provided efficiently and at low cost are: a package for core number ratios appropriate for all types of computers; and dies included in the package. This package includes at least one die provided with: at least one of a first core formed of a CPU core or a latency core and a second core formed of an accelerator core or a throughput core; an external interface; memory interfaces 24 to 26; and a die interface 23 which is connected to another die. The die includes a first type die and a second type die each including both the first core and the second core and the core number ratio between the first core and the second core in the first type die differs from that in the second type die. Moreover, the memory interfaces include an interface conforming to TCI. In addition, the memory interfaces further include an interface conforming to HBM.

A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

A peripheral device controlling device according to an embodiment of the inventive concept includes a command queue for storing at least one Device to Device (D2D) command for data communication between a first peripheral device and a second peripheral device, a command parser for obtaining information related to the data communication from the at least one D2D command, and an orchestrator for controlling at least one of the first peripheral device and the second peripheral device to transfer data from the first peripheral device to the second peripheral device based on the acquired information.

A system and method for communication link management in a credit-based system is disclosed. In one embodiment, a system includes first and second functional circuit blocks implemented on an integrated circuit and being able to communicate with one another through establishment of source synchronous links. The first functional circuit block includes a write queue for storing data and information regarding write requests sent from the second functional circuit block. The write queue includes credit management circuitry arranged to convey one or more credits to the second functional circuit block responsive to receiving one or more write requests therefrom. Responsive to receiving the one or more credits and in the absence of any pending additional requests, the second functional circuit block may deactivate a link with the first functional circuit block.

A system and method for communication link management in a credit-based system is disclosed. In one embodiment, a system includes first and second functional circuit blocks implemented on an integrated circuit and being able to communicate with one another through establishment of source synchronous links. The first functional circuit block includes a write queue for storing data and information regarding write requests sent from the second functional circuit block. The write queue includes credit management circuitry arranged to convey one or more credits to the second functional circuit block responsive to receiving one or more write requests therefrom. Responsive to receiving the one or more credits and in the absence of any pending additional requests, the second functional circuit block may deactivate a link with the first functional circuit block.

A method and technique for allocation and balancing of storage resources includes monitoring, for each of a plurality of storage controllers, an input/output (I/O) latency value based on an I/O latency associated with each storage volume controlled by a respective storage controller. An I/O latency value threshold is determined. Responsive to a change to the I/O latency value exceeding a threshold, storage volume distribution among the storage controllers is rebalanced.

A method and technique for allocation and balancing of storage resources includes monitoring, for each of a plurality of storage controllers, an input/output (I/O) latency value based on an I/O latency associated with each storage volume controlled by a respective storage controller. An I/O latency value threshold is determined. Responsive to a change to the I/O latency value exceeding a threshold, storage volume distribution among the storage controllers is rebalanced.

A method and technique for allocation and balancing of storage resources includes monitoring, for each of a plurality of storage controllers, input/output (I/O) latency, network bandwidth utilization, and network latency associated with each storage volume controlled by a respective storage controller. Responsive to receiving a request to allocate a new storage volume, a type of application and an anticipated storage workload level that will utilize one or more of the storage volumes by the application is determined. The I/O latency, network bandwidth utilization, and network latency is analyzed relative to respective thresholds, and the new storage volume is allocated to a selected storage controller based on the analysis and the anticipated storage workload level.

A method and technique for allocation and balancing of storage resources includes monitoring, for each of a plurality of storage controllers, input/output (I/O) latency, network bandwidth utilization, and network latency associated with each storage volume controlled by a respective storage controller. Responsive to receiving a request to allocate a new storage volume, a type of application and an anticipated storage workload level that will utilize one or more of the storage volumes by the application is determined. The I/O latency, network bandwidth utilization, and network latency is analyzed relative to respective thresholds, and the new storage volume is allocated to a selected storage controller based on the analysis and the anticipated storage workload level.