A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to first connectivity circuitry by a first processor bus and configured to provide first bus transactions to the first processor bus, the discrete signal lines connected to the first connectivity circuitry to provide first discrete signals indicative of discrete events, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert the first bus transactions and the first discrete signals into die-to-die message packets to be communicated to the second connectivity circuitry via a die-to-die interconnect between the first die and the second die, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis.

A computing device can flexibly connect bidirectional processor interconnect ports (BPIPs). An exemplary computing device includes a motherboard structure, a first processor, a second processor, and a plurality of connectors disposed on the motherboard structure. The first processor and the second processor can each have at least three BPIPs. A first and second of BPIPs of the first processor can be connected to a first and second BPIPs of the second processor. A third BPIP of the first processor and a third BPIP of the second processor can be connected to a first one and a second one of the plurality of connectors. The plurality of connectors can be connected to a computing card. In some examples, the computing device includes a switching element to selectively couple the connectors to any other element in the computing device.

A computing device can flexibly connect bidirectional processor interconnect ports (BPIPs). An exemplary computing device includes a motherboard structure, a first processor, a second processor, and a plurality of connectors disposed on the motherboard structure. The first processor and the second processor can each have at least three BPIPs. A first and second of BPIPs of the first processor can be connected to a first and second BPIPs of the second processor. A third BPIP of the first processor and a third BPIP of the second processor can be connected to a first one and a second one of the plurality of connectors. The plurality of connectors can be connected to a computing card. In some examples, the computing device includes a switching element to selectively couple the connectors to any other element in the computing device.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

An authenticating system and process for authenticating user devices to a access a service where access to certain portions of the service may be limited according to a access point or other device used by a user device to facilitate interfacing a user with the service. The authentication may be achieved without directly assessing a trustworthiness of the user devices, and optionally, without requiring a user thereof to complete a sign-on operation.

Message passing circuitry comprises lookup circuitry responsive to a producer request indicating message data provided on a target message channel by a producer node of a system-on-chip, to obtain, from a channel consumer information structure, selected channel consumer information associated with a given consumer node subscribing to the target message channel. Control circuitry writes the message data to a location associated with an address in a consumer-defined region of address space determined based on the selected channel consumer information. When an event notification condition is satisfied for the target message channel and the given consumer node, and an event notification channel is to be used, event notification data is written to a location associated with an address in a consumer-defined region of address space determined based on event notification channel consumer information associated with the event notification channel.

A core suitable for inclusion in an ASIC or other integrated circuit includes a plurality of SPI masters, each of which is able to control and coordinate the timing of a plurality of SPI-controlled devices via an associated SPI bus. Each SPI master is controlled by a corresponding core controller that includes memory, interrupts, flags, timers, and an instruction processor that can independently execute instructions stored in the memory to control data communication between the core controller and its associated SPI master, and between the SPI master and one or more SPI slave devices. The core controllers can be simultaneously started, resynchronized, staggered, and otherwise coordinated with each other. Embodiments further permit bypassing of the core controllers for direct data exchange between external resources and the SPI masters.

A core suitable for inclusion in an ASIC or other integrated circuit includes a plurality of SPI masters, each of which is able to control and coordinate the timing of a plurality of SPI-controlled devices via an associated SPI bus. Each SPI master is controlled by a corresponding core controller that includes memory, interrupts, flags, timers, and an instruction processor that can independently execute instructions stored in the memory to control data communication between the core controller and its associated SPI master, and between the SPI master and one or more SPI slave devices. The core controllers can be simultaneously started, resynchronized, staggered, and otherwise coordinated with each other. Embodiments further permit bypassing of the core controllers for direct data exchange between external resources and the SPI masters.

A control circuit for a switching converter is described herein. In accordance with one embodiment the control circuit includes an analog bus that receives a plurality of input signals and a first set of functional units that are operable to receive at least some of the input signals via the analog bus and to process the input signals to generate digital output data based on the input signals. The control circuit further includes an event bus that has an event bus controller and a plurality of bus lines and a second set of functional units that are operable to receive the output data, via the event bus, from the functional units of the first set. At least one functional unit of the second set of functional units is operable to determine switching time instants for the switching converter based on the output data received via the event bus, and the event bus controller includes an arbiter operable to arbitrate data transmission across the bus lines.