A method and apparatus are provided. The apparatus includes a plurality of central processing units, a plurality of core input/output units, a plurality of last level cache memory banks, an interconnect network comprising multiple instantiations of dedicated data channels, wherein each dedicated data channel is dedicated to a memory transaction type, each instantiation of dedicated data channels includes arbitration multiplexors, and each dedicated data channel operates independently of other data channels.

Systems and methods for processing and arbitrating submission and completion queues are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. The memory device may process the commands based on the determined priority of the command. For example, the memory device may determine a priority for performing the phases after fetching the command. As another example, the memory device may perform the internal command selection based on a priority associated with the command. In this way, commands may be executed based on the priority needs of the memory device or of the host device.

Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

A vehicle safety electronic control system (8) including a first microcontroller (11), a second microcontroller (12), and an inter-processor communication path (13) for bi-directional transfer of data between the microcontrollers (11,12). The system has a first mode of inter-processor communication in which the first microcontroller (11) acts as a master and the second microcontroller (12) acts as a slave, and a second mode of inter-processor communication in which the second microcontroller (12) acts as a master and the first microcontroller (11) acts as a slave. A mode selector (18-20) is provided to select and switch between the first and second modes.

A data transmission chip and an electronic device are provided, and belong to the field of electronic technologies. A low-speed interface of the data transmission chip is configured to receive a plurality of channels of first signals, and a high-speed serial interface of the data transmission chip is configured to serially transmit the plurality of channels of first signals to another data transmission chip in a form of a data frame.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

An example method for simultaneously supporting, on a single VIC adapter (i.e. on a single network interface), RDMA transport according to multiple RoCE versions is disclosed. The method includes providing the VIC adapter with an indication of a RoCE version used for a particular RDMA connection between two compute nodes identified by a certain QP identifier, and then automatically configuring Egress (EG) packet classifier and flow table of the VIC adapter to encapsulate outgoing RDMA commands and automatically configuring Ingress (IG) packet classifier and flow table of the VIC adapter to decapsulate incoming RoCE packets for that RDMA connection according to the indicated RoCE version. Automatic encapsulation and decapsulation according to any one of the multiple RoCE versions that may be used for a particular RDMA connection, i.e. on a per-QP basis, advantageously allows co-existence of routable (i.e. RoCEv2) and non-routable (i.e. RoCEv1) RDMA solutions on a single network interface.

Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.

Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.