Patent classifications
G06F15/17
Parallel-serial conversion circuit, information processing apparatus and timing adjustment method
A parallel-serial conversion circuit including a data transmission unit to output first data and second data of a prescribed pattern in accordance with a second clock obtained by dividing a first clock, a first flip flop to receive the first data so as to output the first data in accordance with the first clock, a second flip flop to receive the second data so as to output the second data in accordance with the first clock, a selector to select one of the first data and the second data so as to output the selected data in accordance with the first clock, and an adjustment unit to compare the second data to be received by the second flip flop and the first data output from the first flip flop so as to adjust, based on a comparison result, a timing for the first flip flop to receive the first data.
CLICKSTREAM ANALYSIS METHODS AND SYSTEMS RELATED TO IMPROVEMENTS IN ONLINE STORES AND MEDIA CONTENT
Methods and systems are provided herein for the analysis of information about online actions of a plurality of users. The analysis methods and systems allow for the modification of online and offline business operations and marketing communications based on online consumer behavior. The methods and systems may obtain an input data set comprising information about online actions of a plurality of users, process the input data set to obtain transformed clickstream data, analyze the transformed clickstream data to identify an order in which each user of the plurality of users views a plurality of product offerings, determine an average order position that a specific product offering of the plurality of product offerings is viewed, and modify an offline or online marketing communication associated with the specific product offering based on the average order position of the specific product offering.
Multiprocessing subsystem with FIFO/buffer modes for flexible input/output processing in an emulation system
In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation. Channels of multiple buffers and associated processors provide implement read and write instructions received at the interface. Multiple access modes are provided to read and write to system memory and to store sequences of commands in the provided buffers and to execute those stored sequences using an associated processor. By writing a sequence of commands and/or data blocks to the channel buffers, the associated processors can execute programs of varying complexity that may have been written or modified in real time or preconfigured.
System and method for generating graphical user interface
An automated method for generating Graphical User Interfaces (GUI's) is illustrated in the context of a system for processing financial applications. In one embodiment, the GUI generator converts domain data representing over one thousand application types into an equal number of corresponding user screens. The interface may also be bi-directional, operating on user inputs to validate data or check for double keying.
Masking a power state of a core of a processor
In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.
RECONFIGURABLE INTERCONNECTED PROGRAMMABLE PROCESSORS
A plurality of software programmable processors is disclosed. The software programmable processors are controlled by rotating circular buffers. A first processor and a second processor within the plurality of software programmable processors are individually programmable. The first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors. The first processor sends and receives data from the neighbor processors. The first processor and the second processor are configured to operate on a common instruction cycle. An output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle.
Method and apparatus for write-only inter-processor reset synchronization
A method and apparatus is disclosed herein for performing write-only inter processor reset synchronization. In one embodiment, the processing unit comprises: a communication unit to transmit information to the second processing unit; memory to store reset synchronization information and message information; and processing logic to perform write-only reset synchronization between itself and the second processing unit based on bit indications set in the memory.
Method and apparatus for write-only inter-processor reset synchronization
A method and apparatus is disclosed herein for performing write-only inter processor reset synchronization. In one embodiment, the processing unit comprises: a communication unit to transmit information to the second processing unit; memory to store reset synchronization information and message information; and processing logic to perform write-only reset synchronization between itself and the second processing unit based on bit indications set in the memory.
Clickstream analysis methods and systems related to improvements in online stores and media content
Methods and systems are provided herein for the analysis of information about online actions of a plurality of users. The analysis methods and systems allow for the creation of new online and offline business methods based on online consumer behavior. The methods and systems may obtain an input data set comprising information about online actions of a plurality of users, convert the input data set into data files having a common file format with each data file corresponding to a user of the plurality of users and comprising an identifier for the user and a plurality of Uniform Resource Locations (URLs) associated with online actions of the user, access online information relating to search terms and webpages, and determine one or more metrics of user behavior, including a verticals metric and a search terms metric.
Clickstream analysis methods and systems related to improvements in online stores and media content
Methods and systems are provided herein for the analysis of information about online actions of a plurality of users. The analysis methods and systems allow for the creation of new online and offline business methods based on online consumer behavior. The methods and systems may obtain an input data set comprising information about online actions of a plurality of users, convert the input data set into data files having a common file format with each data file corresponding to a user of the plurality of users and comprising an identifier for the user and a plurality of Uniform Resource Locations (URLs) associated with online actions of the user, access online information relating to search terms and webpages, and determine one or more metrics of user behavior, including a verticals metric and a search terms metric.