Methods, apparatus, and software for optimizing network data flows within constrained systems. The methods enable data to be transferred between PCIe cards in multi-socket server platforms, each platform including a local socket having an InfiniBand (IB) HCA and a remote socket. Data to be transmitted outbound from a platform is transferred from a PCIe card to the platform's IB HCA via a proxied datapath. Data received at a platform may employ a direct PCIe peer-to-peer (P2P) transfer if the destined PCIe card is installed in the local socket or via a proxied datapath if the destined PCIe card is installed in a remote socket. Outbound transfers from a PCIe card in a local socket to the platform's IB HCA may selectively be transferred using an either a proxied data path for larger data transfers or a direct P2P datapath for smaller data transfers. The software is configured to support each of local-local, remote-local, local-remote, and remote-remote data transfers in a manner that is transparent to the software applications generating and receiving the data.

Methods, apparatus, and software for optimizing network data flows within constrained systems. The methods enable data to be transferred between PCIe cards in multi-socket server platforms, each platform including a local socket having an InfiniBand (IB) HCA and a remote socket. Data to be transmitted outbound from a platform is transferred from a PCIe card to the platform's IB HCA via a proxied datapath. Data received at a platform may employ a direct PCIe peer-to-peer (P2P) transfer if the destined PCIe card is installed in the local socket or via a proxied datapath if the destined PCIe card is installed in a remote socket. Outbound transfers from a PCIe card in a local socket to the platform's IB HCA may selectively be transferred using an either a proxied data path for larger data transfers or a direct P2P datapath for smaller data transfers. The software is configured to support each of local-local, remote-local, local-remote, and remote-remote data transfers in a manner that is transparent to the software applications generating and receiving the data.

Methods, systems, and media for providing content are provided. In some implementations, methods for providing content are provided, the methods comprising: identifying, using a hardware processor, a first content provider; identifying a second content provider affiliated with the first content provider; identifying an item of content associated with the second content provider, and determining that the content item meets one or more parameters of the first content provider and that the content item meets one or more parameters of the second content provider; and in response to determining that the content item meets one or more parameters of the first content provider and that the content item meets one or more parameters of the second content provider, presenting the content item to a user.

Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip (HSIC) interface are disclosed. In one exemplary embodiment, a device-initiated and host-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

Apparatuses, systems, and methods for dual processor single board computers are provided. For example, a dual processor single board computer may include a management processor with associated memory, an application co-processor with associated memory, and a plurality of bus switches. The dual processor single board computer may be used in devices that may be exposed to radiation, such as satellites. During a radiation event, the management processor may continue operation and isolate the application co-processor and certain memories to cease operation to increase the amount of radiation safely received before damage. After the radiation event, the management processor may reboot the application co-processor, and update applications to allow a device to continue its mission.

Apparatuses, systems, and methods for dual processor single board computers are provided. For example, a dual processor single board computer may include a management processor with associated memory, an application co-processor with associated memory, and a plurality of bus switches. The dual processor single board computer may be used in devices that may be exposed to radiation, such as satellites. During a radiation event, the management processor may continue operation and isolate the application co-processor and certain memories to cease operation to increase the amount of radiation safely received before damage. After the radiation event, the management processor may reboot the application co-processor, and update applications to allow a device to continue its mission.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

The disclosure relates to a computing apparatus, for parallel computing, a method, a system, and a non-transitory computer readable media. The computing apparatus comprises a plurality of microcontrollers, including a master microcontroller and at least two slave microcontrollers. The computing apparatus comprises a bus, operatively interconnecting the plurality of microcontrollers. The computing apparatus comprises an input/output (I/O) interface operatively interconnected to the master microcontroller. The computing apparatus comprises a power supply. The master microcontroller is operative to receive executable fdes through the I/O interface, to distribute the executable fdes to the at least two slave microcontrollers, to receive a response from the at least two slave microcontrollers and to transmit an aggregated response through the I/O interface.

The disclosure relates to a computing apparatus, for parallel computing, a method, a system, and a non-transitory computer readable media. The computing apparatus comprises a plurality of microcontrollers, including a master microcontroller and at least two slave microcontrollers. The computing apparatus comprises a bus, operatively interconnecting the plurality of microcontrollers. The computing apparatus comprises an input/output (I/O) interface operatively interconnected to the master microcontroller. The computing apparatus comprises a power supply. The master microcontroller is operative to receive executable fdes through the I/O interface, to distribute the executable fdes to the at least two slave microcontrollers, to receive a response from the at least two slave microcontrollers and to transmit an aggregated response through the I/O interface.