Methods and systems are proposed for a communication network. In one example, a system comprises a wireless communication network comprising a verification logic hardware. The system further comprises a processor of a vehicle communicatively coupled to the verification logic hardware, wherein the processor comprises instructions stored on non-transitory memory thereof that when executed enable the processor to determine a message type of a message, and distribute the message to a first queue of a verification logic software of the processor or to a second queue of the verification logic hardware.

A signal processing device and a vehicle communication device including the same are disclosed. The signal processing device according to an embodiment of the present disclosure includes: a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme; a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme; and a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor. Accordingly, it is possible to reduce latency and to perform high-speed data transmission during inter-processor communication.

A signal processing device and a vehicle communication device including the same are disclosed. The signal processing device according to an embodiment of the present disclosure includes: a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme; a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme; and a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor. Accordingly, it is possible to reduce latency and to perform high-speed data transmission during inter-processor communication.

The present application relates to a dynamic self-adaptive virtual channel mapping method and apparatus, and a storage medium. The method includes: monitoring equivalent data flows of transaction layer packets of different transmit classes, and obtaining the sum of the equivalent data flows of all the transmit classes, the equivalent data flow being the product of a data length of the transaction layer packet and a coefficient; obtaining a pre-calculation value of the number of virtual channels corresponding to each transmit class base on the sum of the equivalent data flows of the transmit classes; and adjusting mapping from the transmit classes to the virtual channels according to the pre-calculation value to obtain a mapping relationship table from the transmit classes to the virtual channels.

The present application relates to a dynamic self-adaptive virtual channel mapping method and apparatus, and a storage medium. The method includes: monitoring equivalent data flows of transaction layer packets of different transmit classes, and obtaining the sum of the equivalent data flows of all the transmit classes, the equivalent data flow being the product of a data length of the transaction layer packet and a coefficient; obtaining a pre-calculation value of the number of virtual channels corresponding to each transmit class base on the sum of the equivalent data flows of the transmit classes; and adjusting mapping from the transmit classes to the virtual channels according to the pre-calculation value to obtain a mapping relationship table from the transmit classes to the virtual channels.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for managing an interface between a pair of processing cores of a device that are configured to exchange data. The device is configured to enable or disable one or more of the pair of processing cores. One of the methods includes configuring a connect/disconnect interface implemented as logic circuitry between the pair of processing cores to assume a connected state in which the pair of processing cores and exchange data, and configuring the connect/disconnect interface between the pair of processing cores to assume a disconnected state in which one or more of the processing cores is unable to receive data.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for managing an interface between a pair of processing cores of a device that are configured to exchange data. The device is configured to enable or disable one or more of the pair of processing cores. One of the methods includes configuring a connect/disconnect interface implemented as logic circuitry between the pair of processing cores to assume a connected state in which the pair of processing cores and exchange data, and configuring the connect/disconnect interface between the pair of processing cores to assume a disconnected state in which one or more of the processing cores is unable to receive data.

A signal processing device and a vehicle communication device including the same are disclosed. The signal processing device according to an embodiment of the present disclosure includes: a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme; a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme; and a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor. Accordingly, it is possible to reduce latency and to perform high-speed data transmission during inter-processor communication.

A signal processing device and a vehicle communication device including the same are disclosed. The signal processing device according to an embodiment of the present disclosure includes: a first processor configured to receive a first message including a sensor signal in a vehicle based on a first communication scheme; a second processor configured to receive a second message including a communication message received from an external source based on a second communication scheme; and a shared memory configured to operate to transmit the first message or the second message between the first processor and the second processor. Accordingly, it is possible to reduce latency and to perform high-speed data transmission during inter-processor communication.