The present disclosure provides an on-chip communication system for neural network processors, a processing device, and a method for operating on an on-chip communication system. The system can include a cluster manager configured to generate a global signal, and a plurality of tile units in a tile array coupled with the cluster manager, each including two connectors and a node connected between the two connectors.

A method is provided in one example embodiment and includes detecting by a first network element at a first data center site a local connection of an endpoint identifier (“EID”), in which the EID was previously locally connected to a second network element at a second data center site and notifying a mapping server of the local connection of the EID to the first network element. The method further includes receiving from the mapping server identifying information for the second network element and communicating with the second network element using the identifying information to obtain service information for traffic associated with the EID. The method may also include applying a service identified by the service information to outgoing traffic from the EID as well as applying a service identified by the service information to incoming traffic for the EID.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

A circuit system includes slow running logic circuitry that generates write data and a write command for a write request. The circuit system also includes fast running logic circuitry that receives the write data and the write command from the slow running logic circuitry. The fast running logic circuitry stores the write data and the write command. A host system generates a write response in response to receiving the write command from the fast running logic circuitry. The host system sends the write response to the fast running logic circuitry. The fast running logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the slow running logic circuitry.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

An electronic device and a power control method of an electronic device are provided. The electronic device may include: a communication circuit including a first circuit configured to perform first communication and a second circuit configured to perform second communication; a processor electrically connected to the communication circuit; and a memory electrically connected to the processor, wherein, the memory stores instructions that, when executed, cause the processor to perform operations comprising: controlling the first circuit to operate according to a first power control mode associated with the first communication, and controlling the second circuit to operate according to a second power control mode associated with the second communication when the first communication and the second communication are concurrently performed through the first circuit and the second circuit; identifying a first sleep period during which the first circuit operates in a sleep mode according to the first power control mode, and a second sleep period during which the second circuit operates in the sleep mode according to the second power control mode; and controlling the communication circuit to operate in a deep sleep mode in which the communication circuit operates with power that is less than or equal to a predetermined power in a period where the first sleep period and the second sleep period coincide.

An electronic device and a power control method of an electronic device are provided. The electronic device may include: a communication circuit including a first circuit configured to perform first communication and a second circuit configured to perform second communication; a processor electrically connected to the communication circuit; and a memory electrically connected to the processor, wherein, the memory stores instructions that, when executed, cause the processor to perform operations comprising: controlling the first circuit to operate according to a first power control mode associated with the first communication, and controlling the second circuit to operate according to a second power control mode associated with the second communication when the first communication and the second communication are concurrently performed through the first circuit and the second circuit; identifying a first sleep period during which the first circuit operates in a sleep mode according to the first power control mode, and a second sleep period during which the second circuit operates in the sleep mode according to the second power control mode; and controlling the communication circuit to operate in a deep sleep mode in which the communication circuit operates with power that is less than or equal to a predetermined power in a period where the first sleep period and the second sleep period coincide.

A system includes a memory, an interface engine, and a master. The memory is configured to store data. The inference engine is configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data. The master is configured to interleave an address associated with memory access transaction for accessing the memory. The master is further configured to provide a content associated with the accessing to the inference engine.