A computer system includes a BMC and a host of the BMC. The BMC redirect, through a BMC communication channel, a local media including a disk management tool to a host of the BMC as a particular drive. The host is a storage device connected to one or more storage drives. The disk management tool is configured to prepare a storage area of the one or more storage drives for installation of storage service on the host. The storage service managing a RDMA controller at the host. The BMC configures the host to boot from the particular drive. The BMC sends a first instruction to the host instructing the BMC to reboot. The BMC receives from the host a command for reading the disk management tool. The BMC sends the disk management tool to the host.

A multi-element problem may be solved iteratively by using a modified genetic algorithm to generate a plurality of solutions according to a set of solution criteria. The solution criteria may comprise a plurality of servers, each server including one or more attributes, and an indication of which of the one or more attributes are to be optimized. An index may be appended, by a processing device, to each solution in the plurality of solutions and the values in each solution may be sorted. For each solution in the plurality of solutions, one or more values from the solution may be combined with one or more values from another solution to generate a plurality of child solutions. Each child solution may have an index, and the values in each child solution may be sorted in view of the child solution's index. For one or more child solutions in the plurality of child solutions, two selected values may be rearranged to generate one or more mutated child solutions.

Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.

One example provides an integrated computing device, comprising one or more computing clusters, and one or more network controllers, each network controller comprising a local data notification queue to queue send message notifications originating from the computing clusters on the integrated computing device, a remote data notification queue to queue receive message notifications originating from network controllers on remote integrated computing devices, a local no-data notification queue to queue receive message notifications originating from computing clusters on the integrated computing device, and a connection scheduler configured to schedule sending of data from memory on the integrated computing device when a send message notification in the local data notification queue is matched with a receive message notification in the remote data notification queue, and to schedule sending of receive message notifications from the local no-data notification queue.

A communication control device, includes a memory; and a processor coupled to the memory and the processor configured to: store, in the memory, instructions of standby processing in a specific processing order, when a network coupling is being established to perform communication, acquire a specific instructions, update, in the memory, the instructions of standby processing based on a type of the specific instructions, a type of the instructions of standby processing and a relationship specified by order in which the specific instructions are acquired, and after an establishment of the network coupling is completed, perform the instructions of standby processing in a specific processing order.

A communication control device, includes a memory; and a processor coupled to the memory and the processor configured to: store, in the memory, instructions of standby processing in a specific processing order, when a network coupling is being established to perform communication, acquire a specific instructions, update, in the memory, the instructions of standby processing based on a type of the specific instructions, a type of the instructions of standby processing and a relationship specified by order in which the specific instructions are acquired, and after an establishment of the network coupling is completed, perform the instructions of standby processing in a specific processing order.

Described herein are method and apparatus for servicing software components of nodes of a cluster storage system. During data-access sessions with clients, client IDs and file handles for accessing files are produced and stored to clients and stored (as session data) to each node. A serviced node is taken offline, whereby network connections to clients are disconnected. Each disconnected client is configured to retain its client ID and file handles and attempt reconnections. Session data of the serviced node is made available to a partner node (by transferring session data to the partner node). After clients have reconnected to the partner node, the clients may use the retained client IDs and file handles to continue a data-access session with the partner node since the partner node has access to the session data of the serviced node and thus will recognize and accept the retained client ID and file handles.

An information handling system includes a processor and a hardware device. The hardware device includes a first engine to provide a first operation on data, and a second engine to provide a second operation on data. The processor provides a command to the hardware device. The command directs the first engine to perform the first operation on first data to create second data based upon the performance of the first operation on the first data, and directs the second engine to perform the second operation on the second data to create third data based upon the performance of the second operation on the second data in response to a completion signal. The hardware device is configured to provide the completion signal to the second engine when the performance of the first operation on the first data is completed.

An electronic device includes a requester and a link interface coupled between the requester and a link. The requester is configured to send a request packet to a completer on the link via the link interface. When sending the request packet to the completer, the requester sends, to the completer via the link interface, the request packet with a tag that is not unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer before the request packet is in the internal elements of the completer, but that is unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer while the request packet is in the internal elements of the completer.

Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.