An FPGA-based USB3.0/3.1 control system, including: a USB control module including a USB3.0 control module and/or a USB3.1 control module; a PCS logic module connected to the USB control module via a PIPE interface; an FPGA Serdes serial communication module connected to the PCS logic module; and an external daughter card module connected to the FPGA Serdes serial communication module, wherein the PCS logic module, the FPGA Serdes serial communication module and the external daughter card module are connected in sequence to achieve a port physical layer function for testing the USB 3.0 control module and the USB 3.1 control module. The control system solves the cumbersome problems of incomplete emulation verification, test mode limitations, and unchangeable hardware functions in the prior art.

A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

An apparatus includes a plurality of subsystems, including a first subsystem and a second subsystem. The apparatus includes a master processor to, in response to a power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions. The apparatus further includes a slave processor to, prior to the boot of the apparatus, receive the second instructions from the master processor and execute the second instructions to configure the second subsystem.

In some examples, an Internet of Things (IoT) apparatus including a plurality of boards and one or more connectors to couple IoT modules to one or more of the plurality of boards and to couple the plurality of boards to each other. The connectors include stacking connectors on both sides of at least some of the boards and at least some of the IoT modules to be coupled to the boards. The stacking connectors allow the IoT modules and the boards to be coupled together in a manner that boards and modules cannot be inserted incorrectly.

A mainboard and a server are provided. The mainboard includes: a board body, a preset number of Purley platform central processors, and one or more memories. The preset number of Purley platform central processors and the one or more memories are installed on the board body. The Purley platform central processors are sequentially connected with each other, and each of the memories is connected to one of the Purley platform central processors. Each of the memories is configured to receive to-be-burned data inputted from outside and transmit the to-be-burned data to the Purley platform central processor connected with the memory. Each of the Purley platform central processors is configured to burn the to-be-burned data when receiving the to-be-burned data transmitted by the connected memory connected with the Purley platform central processor, to have a function corresponding to the to-be-burned data.

An apparatus includes a plurality of subsystems, including a first subsystem and a second subsystem. The apparatus includes a master processor to, in response to a power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions. The apparatus further includes a slave processor to, prior to the boot of the apparatus, receive the second instructions from the master processor and execute the second instructions to configure the second subsystem.

A computer system includes a processor and a memory. The processor is located on a first circuit board having a first connector. The memory is located on a second circuit board having a second connector. The first circuit board and the second board are physically separated from each other but connect to each other through the connector. The processor and the memory are communicated to each other based on a differential signaling scheme.

A computer system, including a computing module, a communication module, and at least one I/O interface is described. The computing module includes a COM Express module and/or a COM HPC module. The communication module includes a SMARC module and/or a Qseven module. The communication module has an FPGA module which is connected in a signal-transmitting manner to the computing module and to the at least one I/O interface. The FPGA module is configured to communicate with the computing module based on at least one first communication standard, and to communicate with the at least one I/O interface based on at least one second communication standard. The FPGA module is configured to convert signals from the least one first communication standard to the at least one second communication standard and vice versa. The computing module is configured as a host, and the communication module is configured as a client. A method of operating a computer system is furthermore described.

The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

The approach relates to a modular computer architecture of a cockpit and infotainment system for a vehicle that includes an I/O module with an I/O computing node (2.0) with at least one data memory, the I/O computing node being designed for processing audio data and as a host computer for performing host functions with ASIL safety requirements. The I/O module also includes a tuner with associated antenna interface, and at least one interface of a vehicle bus system. The modular computer architecture further includes at least one computing module with a computing node with at least one data memory for performing cockpit and infotainment functions, and at least one display interface.