An exemplary plurality of system nodes is arranged in a multi-stage modular architecture. A first system node performs a first frame processing task on a first frame of a frame sequence, and a second system node performs a second frame processing task on a second frame of the frame sequence. The first and second system nodes are included respectively, within first and second pipeline stages of the multi-stage modular architecture, and the first and second frame processing tasks are associated with the respective first and second pipeline stages. Subsequent to performing the first and second frame processing tasks, the first and second system nodes transmit the first and second frames to additional system nodes included within subsequent pipeline stages of the multi-stage modular architecture. These transmissions are synchronized so as to be performed within a predetermined threshold time of one another. Corresponding systems and methods are also disclosed.

A reconfigurable computing appliance includes a number of computing tiles. Each computing tile includes a reconfigurable processing element and a network fabric interface device configured to communicate over a network fabric. The reconfigurable processing element operates on data received from an I/O input interface and/or data received via the network fabric interface device.

Apparatus and methods for processing neural network models are provided. The apparatus can comprise a plurality of identical artificial intelligence processing dies. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies can include at least one inter-die input block and at least one inter-die output block. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies corresponds to at least one layer of a neural network.

One example method includes transmitting, by an application running in a host CPU, a notification to an application in a coprocessor/accelerator indicating that inbound data generated by the application is ready, receiving, by the application in the coprocessor/accelerator, the notification and delegating, by the application in the coprocessor/accelerator, an IO command to the application running in the host CPU, forwarding, by the application running in the host CPU, the IO command to an OS of the host CPU, transmitting, by the OS of the host CPU, an IO request to an IO device, initiating, by the IO device, a P2PDMA to transmit data associated with the IO request to a memory of the coprocessor/accelerator, and processing, by the application in the coprocessor/accelerator, the data.

One example method includes transmitting, by an application running in a host CPU, a notification to an application in a coprocessor/accelerator indicating that inbound data generated by the application is ready, receiving, by the application in the coprocessor/accelerator, the notification and delegating, by the application in the coprocessor/accelerator, an IO command to the application running in the host CPU, forwarding, by the application running in the host CPU, the IO command to an OS of the host CPU, transmitting, by the OS of the host CPU, an IO request to an IO device, initiating, by the IO device, a P2PDMA to transmit data associated with the IO request to a memory of the coprocessor/accelerator, and processing, by the application in the coprocessor/accelerator, the data.

An example system may comprise a network-attached storage device including a base station having a hardware interface including a drive port and a connectivity port; a modular storage drive attachable to and detachable from the drive port; and a modular wireless adapter attachable to and detachable from the connectivity port. The portable storage device is formable by detaching the modular storage drive and the modular wireless adapter from the hardware interface of the network-attached storage device, and coupling the modular storage drive and the modular wireless adapter to one another via a portable hardware interface. Further, a rechargeable modular power unit is removable from the base station and attachable to and detachable from a power port of the network-attached storage device.

An example system may comprise a network-attached storage device including a base station having a hardware interface including a drive port and a connectivity port; a modular storage drive attachable to and detachable from the drive port; and a modular wireless adapter attachable to and detachable from the connectivity port. The portable storage device is formable by detaching the modular storage drive and the modular wireless adapter from the hardware interface of the network-attached storage device, and coupling the modular storage drive and the modular wireless adapter to one another via a portable hardware interface. Further, a rechargeable modular power unit is removable from the base station and attachable to and detachable from a power port of the network-attached storage device.

A reconfigurable computing appliance includes a number of computing tiles. Each computing tile includes a reconfigurable processing element and a network fabric interface device configured to communicate over a network fabric. The reconfigurable processing element operates on data received from an I/O input interface and/or data received via the network fabric interface device.

Provided efficiently and at low cost are: a package for core number ratios appropriate for all types of computers; and dies included in the package. This package includes at least one die provided with: at least one of a first core formed of a CPU core or a latency core and a second core formed of an accelerator core or a throughput core; an external interface; memory interfaces 24 to 26; and a die interface 23 which is connected to another die. The die includes a first type die and a second type die each including both the first core and the second core and the core number ratio between the first core and the second core in the first type die differs from that in the second type die. Moreover, the memory interfaces include an interface conforming to TCI. In addition, the memory interfaces further include an interface conforming to HBM.

A computer system includes a processor and a memory. The processor is located on a first circuit board having a first connector. The memory is located on a second circuit board having a second connector. The first circuit board and the second board are physically separated from each other but connect to each other through the connector. The processor and the memory are communicated to each other based on a differential signaling scheme.