A resistor mesh with distributed sensing points is provided in a security chip as an anti-tamper shield. An analog multiplexing circuit is configured to receive a pair of digital selection values created by an algorithm processing circuit, and produce a respective differential voltage formed by a pair of voltages obtained at a pair of selected sensing points within the resistor mesh corresponding to the pair of digital selection values. Each differential voltage is converted into a corresponding digital output value. An algorithm processing circuit is configured to receive a respective digital output value associated with each pair of digital selection values and derive a binary value based on a subset of the digital output values, wherein the binary value is unique to the security chip.

Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing tamper detections in secure memory devices. In one aspect, a secure memory device includes: a memory cell array, one or more tamper detectors each configured to detect a respective type of tamper event on at least part of the secure memory device, and a tamper detection status register storing one or more values each indicating a tamper detection status detected by a corresponding tamper detector. The secure memory device can include a command interface coupled to the tamper detection status register and configured to output the values stored in the tamper detection status register when receiving a trigger. The secure memory device can also include an output pin coupled to the tamper detection status register and be configured to automatically output the values stored in the tamper detection status register via the output pin.

Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing tamper detections in secure memory devices. In one aspect, a secure memory device includes: a memory cell array, one or more tamper detectors each configured to detect a respective type of tamper event on at least part of the secure memory device, and a tamper detection status register storing one or more values each indicating a tamper detection status detected by a corresponding tamper detector. The secure memory device can include a command interface coupled to the tamper detection status register and configured to output the values stored in the tamper detection status register when receiving a trigger. The secure memory device can also include an output pin coupled to the tamper detection status register and be configured to automatically output the values stored in the tamper detection status register via the output pin.

An extended hardware security module (“HSM”) possessing additional security properties relative to conventional HSMs and methods for initializing, deploying, and managing such extended HSMs in a networked environment. In the preferred embodiment, an extended HSM includes additional hardware and software components that configure it to run sensitive client tasks on demand inside a cloud-hosted, anti-tamper HSM housing so as to ensure sensitive data is encrypted when stored or processed outside the housing. Methods for initializing, deploying, and managing provide a framework through which extended HSMs may be secured from their initial assembly through their availing for use and actual use over a network by one or more clients. Such use often entails repeated discrete sequential secure sessions and concurrent discrete secure sessions.

An extended hardware security module (“HSM”) possessing additional security properties relative to conventional HSMs and methods for initializing, deploying, and managing such extended HSMs in a networked environment. In the preferred embodiment, an extended HSM includes additional hardware and software components that configure it to run sensitive client tasks on demand inside a cloud-hosted, anti-tamper HSM housing so as to ensure sensitive data is encrypted when stored or processed outside the housing. Methods for initializing, deploying, and managing provide a framework through which extended HSMs may be secured from their initial assembly through their availing for use and actual use over a network by one or more clients. Such use often entails repeated discrete sequential secure sessions and concurrent discrete secure sessions.

Provided is an anti-tamper protection circuit including a switch trigger port, a tamper signal transmission port, a power supply unit, and a signal output port. The switch trigger port is connected to a switch, the signal output port is connected to a digital movie server, and the tamper signal transmission port is configured to transmit a tamper signal transmitted to the signal output port through the tamper signal transmission port. In the present disclosure, when an LED display screen is powered off, a battery inside the digital cinema server would continue to power the digital cinema server to maintain proper functioning of the digital cinema server, the power supply unit also powers the anti-tamper protection circuit to guarantee anti-tamper operation of the anti-tamper protection circuit, thereby enabling continuous protection of information security and maintenance of digital copyright, and such that the requirements of information handling standards are satisfied.

An embodiment of an IC is provided. The IC includes a memory, a controller, an intrusion detector and a memory clear circuit. The memory is configured to store sensitive data. The controller is configured to access the memory. The intrusion detector is configured to detect whether an intrusion event is present in response to an input signal. The memory clear circuit is configured to clear the sensitive data of the memory when the intrusion detector detects the intrusion event.

Embodiments of systems are disclosed herein to detect tampering and/or provide evidence of tampering without human interaction or oversight. In the disclosed embodiments, tampering is detected and tamper evidence is provided by incorporating at least one tamper-evident assembly and at least one processing device within an enclosure. The tamper-evident assembly includes a tamper-evident fastener having an integrated circuit (IC) chip, which is embedded within the tamper-evident fastener and configured to transmit a data signal through the tamper-evident fastener to the at least one processing device when the tamper-evident fastener is coupled to a surface of the enclosure to secure a point of entry on the enclosure. In some embodiments, the at least one processing device is configured to detect tampering and/or provide evidence of tampering when the data signal transmitted from the IC chip is not received.

Embodiments of systems are disclosed herein to detect tampering and/or provide evidence of tampering without human interaction or oversight. In the disclosed embodiments, tampering is detected and tamper evidence is provided by incorporating at least one tamper-evident assembly and at least one processing device within an enclosure. The tamper-evident assembly includes a tamper-evident fastener having an integrated circuit (IC) chip, which is embedded within the tamper-evident fastener and configured to transmit a data signal through the tamper-evident fastener to the at least one processing device when the tamper-evident fastener is coupled to a surface of the enclosure to secure a point of entry on the enclosure. In some embodiments, the at least one processing device is configured to detect tampering and/or provide evidence of tampering when the data signal transmitted from the IC chip is not received.

An integrated circuit including an input terminal and an output terminal, signal generator circuitry that generates a pseudo-random digital signal provided at the output terminal, and comparator circuitry that compares an input signal received via the input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof. The signal generator circuitry may be a pseudo-random binary sequence generator or may be a linear-feedback shift register with software triggered reloading. The comparator circuitry may include a Boolean logic exclusive-OR gate for comparing the output and input signals. A method of detecting tampering including generating and providing a pseudo-random digital signal at an output terminal and comparing an input signal received via an input terminal with the pseudo-random digital signal for providing a tamper detection signal indicative thereof.