The present disclosure provides a method for generating a spatially resolved netlist that includes generating a netlist based on integrated circuit (IC) layout data and standard cell library data, the netlist including cell and net definitions associated with the IC; determining position data for respective cells and nets based on the IC layout data; mapping the position data to respective cell and net definitions in the netlist; and generating a spatially resolved netlist that includes the mapped position data to respective cell and net definitions.

The present disclosure provides a method for generating a spatially resolved netlist that includes generating a netlist based on integrated circuit (IC) layout data and standard cell library data, the netlist including cell and net definitions associated with the IC; determining position data for respective cells and nets based on the IC layout data; mapping the position data to respective cell and net definitions in the netlist; and generating a spatially resolved netlist that includes the mapped position data to respective cell and net definitions.

Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.

Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.

A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.

A method for improving OpenCL hardware execution efficiency described in this invention comprises the following steps: compiling a kernel implemented in OpenCL, generating Verilog code with a high-level synthesis tool; analyzing the interfaces of auto-generated Verilog code, recording signals, timing sequence, and function of the interfaces; manually modifying and optimizing the Verilog code; inserting a file replacement command in the script responsible for flow control, replacing the auto-generated code with the optimized Verilog code; rerunning OpenCL compiler and generating an ultimate FPGA configuration file. The invention makes manual optimization of the auto-generated Verilog code becomes possible, by parsing the compilation flow of OpenCL environment and analyzing the structure and interfaces of the auto-generated Verilog code. It promotes the performance of kernels, by increasing working frequency, achieving more parallelism and taking full advantages of FPGA hardware resources, and improves the execution efficiency of OpenCL on FPGA platform significantly.

A compilation system accesses a compilation operations that can be used by a compiler to compile a design under test (DUT). The compilation system can determine a sequence of the compilation operations for the compiler to perform the compilation. The compilation system can detect a failure at a first compilation operation of the sequence of operations during the compilation of the DUT, and the compilation of the DUT can be paused after the failure is detected. The compilation system can determine a second compilation operation of the accessed compilation operations based on one or more netlist parameters of the DUT's netlist. The compilation system then modifies the sequence of compilation operations based on the second compilation operation and resumes the compilation of the DUT at the second compilation operation using the modified sequence of compilation operations.

A compilation system accesses a compilation operations that can be used by a compiler to compile a design under test (DUT). The compilation system can determine a sequence of the compilation operations for the compiler to perform the compilation. The compilation system can detect a failure at a first compilation operation of the sequence of operations during the compilation of the DUT, and the compilation of the DUT can be paused after the failure is detected. The compilation system can determine a second compilation operation of the accessed compilation operations based on one or more netlist parameters of the DUT's netlist. The compilation system then modifies the sequence of compilation operations based on the second compilation operation and resumes the compilation of the DUT at the second compilation operation using the modified sequence of compilation operations.

This application discloses the implementation of a self-timed IP with optional clock-less compression and decompression at the boundaries. It also discloses system and methods for application specific integrated circuits to convert RTL code and timing constraints to self-timed circuitry with optional clock-less compression and decompression at the boundaries.

An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.