Systems and methods automatically construct a realization of a model from an available set of alternative co-simulation components, where the realization meets one or more objectives, such as fidelity, execution speed, or memory usage, among others. The systems and methods may construct the realization model by setting up and solving a constrained optimization problem, which may select particular ones of the alternative co-simulation components to meet the objectives. The systems and methods may configure the realization, and execute the realized model through co-simulation. The systems and methods may employ and manage different execution engines and/or different solvers to run the realization of the model.

Described is a configuration to remove false paths from an emulation netlist in a chip design under test (DUT). The configuration identifies, in an original netlist, an original subgraph of original logic gates, a subset of inputs (TI), and a subset of outputs (TO). The configuration generates a replicated subgraph of the original subgraph, the replicated subgraph having replicated logic gates corresponding to the original logic gates. The configuration connects the TI with a first replicated logic gate to a constant propagation source and remaining inputs of the replicated logic gates with corresponding original logic gates in the original netlist. The configuration disconnects, in the original netlist, output loads of TO, and connects the output loads of TO with a corresponding equivalent TO in the replicated subgraph. The configuration deletes, in the original netlist, original logic gates unconnected with an output load for TO in the original netlist.

Described is a configuration to remove false paths from an emulation netlist in a chip design under test (DUT). The configuration identifies, in an original netlist, an original subgraph of original logic gates, a subset of inputs (TI), and a subset of outputs (TO). The configuration generates a replicated subgraph of the original subgraph, the replicated subgraph having replicated logic gates corresponding to the original logic gates. The configuration connects the TI with a first replicated logic gate to a constant propagation source and remaining inputs of the replicated logic gates with corresponding original logic gates in the original netlist. The configuration disconnects, in the original netlist, output loads of TO, and connects the output loads of TO with a corresponding equivalent TO in the replicated subgraph. The configuration deletes, in the original netlist, original logic gates unconnected with an output load for TO in the original netlist.

A method of designing an integrated circuit (IC) device includes identifying, with a processor, a pin failing a test to determine an antenna effect, identifying, with the processor, a net corresponding to the identified pin failing the test to determine the antenna effect, and creating, with the processor, an engineering change order (ECO) script based on the identified net to insert a diode to address the antenna effect.

A method of designing an integrated circuit (IC) device includes identifying, with a processor, a pin failing a test to determine an antenna effect, identifying, with the processor, a net corresponding to the identified pin failing the test to determine the antenna effect, and creating, with the processor, an engineering change order (ECO) script based on the identified net to insert a diode to address the antenna effect.

A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.

A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.

Systems and methods include a method providing automated production optimization for smart well completions using real-time nodal analysis including comingled production calibration. Real-time well rates and flowing bottom-hole pressure data are collected at various choke settings for multiple flow conditions for each lateral of a multilateral well during regular field optimization procedures. Surface and downhole pressures and production metrics for each of the laterals are recorded for one lateral at a time during production of the well. Flowing parameters of individual laterals are estimated using the multilateral well production model. An optimum pressure drop across each downhole valve is determined using the multilateral well production model. Each lateral of the multilateral well is calibrated during the commingled production at various choke valves settings. The calibrating is done using the multilateral well production model, based at least in part on the optimum pressure drop across each downhole valve.

Systems and methods include a method providing automated production optimization for smart well completions using real-time nodal analysis including comingled production calibration. Real-time well rates and flowing bottom-hole pressure data are collected at various choke settings for multiple flow conditions for each lateral of a multilateral well during regular field optimization procedures. Surface and downhole pressures and production metrics for each of the laterals are recorded for one lateral at a time during production of the well. Flowing parameters of individual laterals are estimated using the multilateral well production model. An optimum pressure drop across each downhole valve is determined using the multilateral well production model. Each lateral of the multilateral well is calibrated during the commingled production at various choke valves settings. The calibrating is done using the multilateral well production model, based at least in part on the optimum pressure drop across each downhole valve.

A chip verification system includes a plurality of agent modules, a register model, and a scoreboard module. The register model includes a register database, a plurality of access modules, and a return module. Each access module corresponds to one of a plurality of attribute parameters. Each agent module transmits an address code of its sequence to the return module. The return module obtains, according to the received address code, an address subject and the attribute parameter corresponding to the received address code from the register database, and outputs the obtained attribute parameter. Each driver module calls, according to the received attribute parameter, the corresponding access module to perform an operation on registers of DUT circuit according to a read write command of the sequence. The scoreboard module records each performed operation to generate an operation record, and outputs a verification result according to the operation record and data in registers.