Example embodiments relate to a method for designing integrated circuit based on a computer program including at least one instruction performed by an integrated circuit design system including a processor, the method comprising mapping, by the processor, at least one netlist signal to at least one RTL signal, determining, by the processor, a target netlist signal among the at least one netlist signal, determining, by the processor, a target expression of the target netlist signal using the netlist signal mapped to the at least one RTL signal based on at least a part of the netlist circuit, simulating, by the processor, on the at least one RTL signal, calculating, by the processor, signal simulation predicting information for the target netlist signal using the target expression and generating, by the processor, a design model by designing an integrated circuit using the signal simulation predicting information.

Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method can determine, from a gate level representation of a circuit in a layout on a die of an IC, a first set of paths through the circuit that process security related data during operation of the circuit, the circuit including a second set of paths that do not process security related data; and the method can further determine, in a simulation of power consumption in the first set of paths but not the second set of paths, power consumption values in the first set of paths to determine potential security leakage of the security related data in the circuit. The method can further determine, from the power consumption values, positions in the layout for inserting virtual probes on the die for use in measuring security metrics that indicate potential leakage of the security related data. The insertion of the virtual probes is relative to the actual simulated layout of the die. Other methods, machine readable media and systems are also described.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for optimizing integrated circuit architectures or compiler designs using an optimization engine. The optimization engine includes an auto-encoder and one or more regressors. Once trained, the optimization engine can encode initial, discrete input values of a set of input characteristics into a continuous domain and use continuous optimization techniques to identify final input values of the set of input characteristics that optimize one or more output characteristics.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for optimizing integrated circuit architectures or compiler designs using an optimization engine. The optimization engine includes an auto-encoder and one or more regressors. Once trained, the optimization engine can encode initial, discrete input values of a set of input characteristics into a continuous domain and use continuous optimization techniques to identify final input values of the set of input characteristics that optimize one or more output characteristics.

Systems and methods are provided for designing approximate, low-power deep learning accelerator chips that have little to no accuracy loss when executing a deep learning model. A set of approximate systolic arrays may be generated. The performance of each approximate systolic array in the set of approximate systolic arrays processing a deep neural network (DNN) may be determined. Each layer in the DNN may be mapped to an approximate systolic array in the set of approximate systolic arrays. A subset of the set of approximate systolic arrays may be selected for inclusion in the inference chip design based on the mapping and the performance of each approximate systolic array in the set of approximate systolic arrays.

A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.

Various embodiments provide for clustering-based grouping of cells in a cell library, which can be used for pruning the cell library. In particular, various embodiments provide for a clustering-based grouping of cells in a cell library based on a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for a clustering-based grouping of cells based on leakage power and then applying cell library pruning to optimize for cell leakage power.

Various embodiments provide for clustering-based grouping of cells in a cell library, which can be used for pruning the cell library. In particular, various embodiments provide for a clustering-based grouping of cells in a cell library based on a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for a clustering-based grouping of cells based on leakage power and then applying cell library pruning to optimize for cell leakage power.

A tool makes modifications to the chip floorplan and the network-on-chip (NoC) elements’ position on the floorplan and updates the number and position of the pipeline elements in a pipeline stage automatically, resulting in fewer errors and higher productivity.

Techniques and systems for enhanced adjustment of quantities and placement of decoupling capacitance on circuit boards for integrated circuits is provided herein. An example method includes iterating application of a load profile across different populations of decoupling capacitors on a circuit board for supply voltage domains of an integrated circuit device until a target transient performance is reached for the supply voltage domains. The load profile is applied onto electrical connections corresponding to the supply voltage domains for the integrated circuit device. The method also includes generating a capacitor population configuration for the circuit board based on a population of the decoupling capacitors that achieves the target transient performance.