A method may create RTL for a circuit design utilizing DSP blocks by receiving a software program comprising a multiplication statement to multiply a first number by a second number, the first number having a first data type and a first bit width, the second number having a second data type and a second bit width; determining a number of DSP blocks for implementing the statement based at least on the first bit width, the second bit width, a first DSP bit width corresponding to a bit width of a first operand of the DSP blocks, and a second DSP bit width corresponding to a bit width of a second operand of the DSP blocks, wherein the number of DSP blocks is two or more; and generating RTL for the statement, the RTL comprises a plurality of distinct portions corresponding to each of the two or more DSP blocks.

Fabrication of an electronic circuit is facilitated by providing a computer tool to enhance design of the electronic circuit to meet a design criteria. The computer tool facilitates obtaining one or more hybrid logical entities, where a hybrid logical entity includes a pull-up circuit and a pull-down circuit formed of transistors with different transistor types for pull-up versus pull-down, and different voltage thresholds for pull-up versus pull-down. Further, the facilitating includes incorporating the hybrid logical entity into the electronic circuit design to produce a revised electronic circuit design. The method further includes initiating manufacture of the electronic circuit pursuant, at least in part, to the revised electronic circuit design.

Fabrication of an electronic circuit is facilitated by providing a computer tool to enhance design of the electronic circuit to meet a design criteria. The computer tool facilitates obtaining one or more hybrid logical entities, where a hybrid logical entity includes a pull-up circuit and a pull-down circuit formed of transistors with different transistor types for pull-up versus pull-down, and different voltage thresholds for pull-up versus pull-down. Further, the facilitating includes incorporating the hybrid logical entity into the electronic circuit design to produce a revised electronic circuit design. The method further includes initiating manufacture of the electronic circuit pursuant, at least in part, to the revised electronic circuit design.

Matrix multipliers are computationally complex, and memory intensive algorithms used frequently in a variety of applications, such as deep-learning and scientific computations. Accelerating matrix multiplication involves an inter-play of algorithm-architecture co-design and context-specific design parameters. A performance optimizer intelligently arrives at the right combination of algorithm (203)-architecture specifications (201, 202) for the input design parameters that arrive during real-time for a target-specific design constraint. The run-time customization leads to optimal power-performance-area optimization.

Matrix multipliers are computationally complex, and memory intensive algorithms used frequently in a variety of applications, such as deep-learning and scientific computations. Accelerating matrix multiplication involves an inter-play of algorithm-architecture co-design and context-specific design parameters. A performance optimizer intelligently arrives at the right combination of algorithm (203)-architecture specifications (201, 202) for the input design parameters that arrive during real-time for a target-specific design constraint. The run-time customization leads to optimal power-performance-area optimization.

This disclosure generally relates to high-level synthesis (HLS) platforms, and, more particularly, enable print functionality in high-level synthesis (HLS) platforms. The recent availability FPGA-HLS is a great success due to availability of compilers for FPGAs as opposed to hardware description languages (HDLs) that requires special skills. However, the compilers within the HLS design platform includes limited support for all the standard libraries, wherein features like print functionality is not supported. The invention discloses techniques to enable print functionality in HLS design platforms based on source-to-source transformations and stream combining scheme. In addition to enabling print functionality, the invention also discloses a formatter technique to receive-format FPGA data into human interpretable data.

The present invention discloses a method and system for processing simulation data. The method includes: simultaneously collecting the simulation waveform data of said multiple FPGAs and adding a time stamp to the waveform data of each FPGA collected in each collection period, and storing the waveform data of the multiple FPGAs in the form of a link list according to the time stamp. The technical solution of the present invention can ensure no disorder of the waveform data of multiple FPGAs.

The present invention discloses a method and system for processing simulation data. The method includes: simultaneously collecting the simulation waveform data of said multiple FPGAs and adding a time stamp to the waveform data of each FPGA collected in each collection period, and storing the waveform data of the multiple FPGAs in the form of a link list according to the time stamp. The technical solution of the present invention can ensure no disorder of the waveform data of multiple FPGAs.

The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.

A network device includes processing circuitry configured to: determine whether to initiate a temporal reconfiguration or a spatial reconfiguration of a partial reconfiguration slot on a programmable device, and initiate the temporal reconfiguration or the spatial reconfiguration of the partial reconfiguration slot in response to determining that the temporal reconfiguration or the spatial reconfiguration is to be initiated.