A network device includes processing circuitry configured to: determine whether to initiate a temporal reconfiguration or a spatial reconfiguration of a partial reconfiguration slot on a programmable device, and initiate the temporal reconfiguration or the spatial reconfiguration of the partial reconfiguration slot in response to determining that the temporal reconfiguration or the spatial reconfiguration is to be initiated.

A line diagnosis method includes, in a situation that a first interface of a first device is connected to a second interface of a second device, obtaining first interface information of the first interface and second interface information of the second interface, and diagnosing a line connection between the first device and the second device based on the first interface information and the second interface information.

A line diagnosis method includes, in a situation that a first interface of a first device is connected to a second interface of a second device, obtaining first interface information of the first interface and second interface information of the second interface, and diagnosing a line connection between the first device and the second device based on the first interface information and the second interface information.

The object of the invention is a method of adding another circuit component (1) with operations executable on an FPGA to an FPGA configuration (3), wherein the FPGA configuration (3) already has at least one existing circuit component (2) with operations executable on the FPGA, which is locally distributed in the FPGA configuration (3), with the steps of: Synthesizing the further circuit component (1) to obtain a further netlist, and distributed arranging of the further netlist taking into account the at least one existing circuit component (2) in the FPGA configuration (3).

Various examples are provided related to power side-channel vulnerability assessment. In one example, a method includes identifying target registers in an IC design; generating input patterns associated with a target function that can generate a power difference in the target registers when processing the target function; determining a side-channel vulnerability (SCV) metric using the power difference produced by the input patterns; and identifying a vulnerability in the IC design using the SCV metric. Identification of the vulnerability allows for modification of the IC design at an early stage, which can avoid power side-channel attacks (e.g., DPA and CPA) in the fabricated IC design. The method can be used for pre-silicon power side-channel leakage assessment of IC designs such as, e.g., cryptographic and non-cryptographic circuits.

A circuit system includes a processing circuit, an accelerator circuit, and a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit. The buffer circuit functions as a crossbar circuit by allowing each of the accelerator circuit and the processing circuit to access at least one of the packets of data stored in the buffer circuit during access to another one of the packets of data stored in the buffer circuit.

A manufacturing system design verification device includes a design information model, a design information input part, a verification logic storage part, and a design information verification part. The design information model is a framework integrating and expressing design information. The design information is inputted to the design information input part. The design information input part converts the design information into an expression described a resource description language with reference to the design information model. The verification logic storage part stores a verification logic including a group of a query described in a query language corresponding to the resource description language and an expected result. The design information verification part includes a query execution engine performing the query on the expression an returning an execution result and a comparison engine comparing the execution result with the expected result and returning a verification result.

A field programmable gate array (FPGA) device including a configuration interface arranged to receive configuration data from an FPGA programmer. The FPGA device includes a plurality of random access memory (RAM) types, including a first RAM type and a second RAM type, arranged to store the configuration or image data. The FPGA device also includes a FIFO IP core arranged to implement a FIFO function in a plurality of different FPGA platforms. The FIFO IP core is: i) configured to implement the FIFO in the FPGA device based on the configuration data, and ii) configurable to store the configuration data in one or both of the first RAM type and the second RAM type.

Systems or methods of the present disclosure may provide for determining a load line for operation of a programmable logic fabric where the load line is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The load line may be determined using software modeling for the design or configuration. Additionally or alternatively, the load line may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

Systems or methods of the present disclosure may provide a compilation design method that uses cloud computing resources and/or distributed computing resources to compile initial user designs. The initial user design for the programmable logic device may be partitioned into multiple designs for compilation based on periphery logic and core fabric logic. The compilation design method implements partition-level time budgeting and constraint generation using full device timing analysis. The final placed and routed netlist and bitstream SOF is generated by merging the placed and routed netlist and bitstream SOF of individual partition designs.