Systems or methods of the present disclosure may provide a compilation design method that uses cloud computing resources and/or distributed computing resources to compile initial user designs. The initial user design for the programmable logic device may be partitioned into multiple designs for compilation based on periphery logic and core fabric logic. The compilation design method implements partition-level time budgeting and constraint generation using full device timing analysis. The final placed and routed netlist and bitstream SOF is generated by merging the placed and routed netlist and bitstream SOF of individual partition designs.

An external control FPGA device includes a command receiving terminal configured to receive command data, a control outputting terminal configured to output a functioning control signal, and a plurality of FPGA connection terminals, and a data processing FPGA device that transmits a control command from an external command data receiver to a control signal outputter. The data processing FPGA device is connected to one of the plurality of FPGA connection terminals through a data processing line that is independent of a command transmission pathway including an external command data receiver, a command data line, the external control FPGA device, a functioning control signal line and the control signal outputter. The data processing FPGA device inputs data that is to be processed from the external control FPGA device through the data processing line, and outputs the processed data to the external control FPGA device.

An external control FPGA device includes a command receiving terminal configured to receive command data, a control outputting terminal configured to output a functioning control signal, and a plurality of FPGA connection terminals, and a data processing FPGA device that transmits a control command from an external command data receiver to a control signal outputter. The data processing FPGA device is connected to one of the plurality of FPGA connection terminals through a data processing line that is independent of a command transmission pathway including an external command data receiver, a command data line, the external control FPGA device, a functioning control signal line and the control signal outputter. The data processing FPGA device inputs data that is to be processed from the external control FPGA device through the data processing line, and outputs the processed data to the external control FPGA device.

Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).

Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).

A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.

The present disclosure describes techniques for computation architecture synthesis. Objects may be detected based on source code by a compiler. A type of each object may be identified by the compiler. A plurality of streams each of which corresponds to a particular type of objects among a plurality of types of objects may be defined. A set of operations to be applied to the particular type of objects may be detected. A computational core may be synthesized based on the set of operations. A computational architecture may be synthesized based on the plurality of streams and a plurality of computational cores each of which is associated with at least one of the plurality of streams.

A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.

A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.