An optimizing method, device and non-transient computer readable medium for an integrated circuit layout are provided. The method includes: identifying power rails and corresponding power supply domains in an integrated circuit design file; performing design rule check for circuit units in the integrated circuit design file to calculate a plurality of usable regions; determining electromigration violation points corresponding to the power rails and related current information; defining, according to the electromigration violation points and the current information, paths to be corrected on the power rails corresponding to the electromigration violation points; replacing types of vias on the power rails that do not overlap with the paths to be corrected; and correcting a number of the vias on the power rails that overlap with the paths to be corrected to reduce a number of the electromigration violation points.

An optimizing method, device and non-transient computer readable medium for an integrated circuit layout are provided. The method includes: identifying power rails and corresponding power supply domains in an integrated circuit design file; performing design rule check for circuit units in the integrated circuit design file to calculate a plurality of usable regions; determining electromigration violation points corresponding to the power rails and related current information; defining, according to the electromigration violation points and the current information, paths to be corrected on the power rails corresponding to the electromigration violation points; replacing types of vias on the power rails that do not overlap with the paths to be corrected; and correcting a number of the vias on the power rails that overlap with the paths to be corrected to reduce a number of the electromigration violation points.

Systems, methods, and non-transitory computer-readable storage media for a fast power network simulator. A system configured per this disclosure can use identify a power network, the power network comprising generators, transmission lines, and loads, and receive a model of the power network. The model of the power network can include: models of the generators modeled as differential equations, and models of the transmission lines and the loads modeled as algebraic equations. The system can convert, via a processor, the algebraic equations of the models of the transmission lines and the loads to additional differential equations, then combine, via the processor, the differential equations and the additional differential equations, to yield combined differential equations. The system can then iteratively solve linear equations, via the processor, associated with the combined differential equations, to yield solutions, and output the solutions as part of a power simulation of the power network.

Systems, methods, and non-transitory computer-readable storage media for a fast power network simulator. A system configured per this disclosure can use identify a power network, the power network comprising generators, transmission lines, and loads, and receive a model of the power network. The model of the power network can include: models of the generators modeled as differential equations, and models of the transmission lines and the loads modeled as algebraic equations. The system can convert, via a processor, the algebraic equations of the models of the transmission lines and the loads to additional differential equations, then combine, via the processor, the differential equations and the additional differential equations, to yield combined differential equations. The system can then iteratively solve linear equations, via the processor, associated with the combined differential equations, to yield solutions, and output the solutions as part of a power simulation of the power network.

A true random metastable flip-flop (TRMFF) compiler generates an electrical architecture for a TRMFF chain. The compiler selects components for the TRMFF chain from a library of standard cells and logically connects these components in accordance with a primitive polynomial to generate the electrical architecture. The TRMFF chain provides a sequence of random numbers from one or more physical processes in accordance with the primitive polynomial. During operation, one or more microscopic phenomena inside and/or outside of the TRMFF chain can cause one or more low-level, statistically random entropy noise signals to be present within the TRMFF chain. The TRMFF chain advantageously utilizes the one or more low-level, statistically random entropy noise signals to provide the sequence of random numbers.

A true random metastable flip-flop (TRMFF) compiler generates an electrical architecture for a TRMFF chain. The compiler selects components for the TRMFF chain from a library of standard cells and logically connects these components in accordance with a primitive polynomial to generate the electrical architecture. The TRMFF chain provides a sequence of random numbers from one or more physical processes in accordance with the primitive polynomial. During operation, one or more microscopic phenomena inside and/or outside of the TRMFF chain can cause one or more low-level, statistically random entropy noise signals to be present within the TRMFF chain. The TRMFF chain advantageously utilizes the one or more low-level, statistically random entropy noise signals to provide the sequence of random numbers.

A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

System, methods, and other embodiments described herein relate to determining an improved electrode design of a battery. In one embodiment, a method includes computing one or more equivalent circuits as porous electrode transmission line models corresponding to one or more electrode designs. Individual circuits of the equivalent circuits define an arrangement of electrode elements having at least two geometric degrees of freedom. The electrode designs are defined according to battery specifications indicating at least a battery volume, and a separator thickness. The method includes determining attributes for the equivalent circuits according to the at least the two geometric degrees of freedom in which the equivalent circuits are defined. The method includes identifying a target design of the electrode designs associated with one of or more of the attributes satisfying a circuit threshold. The target design improves one or more of the attributes in relation to the battery.

A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.