Embodiments of the present application provide a memory array circuit, a memory array layout and a verification method. The memory array circuit includes: M word lines (WLs); M WL break nodes, each being configured to separate a corresponding one of the WLs into a first WL pin and a second WL pin; N bit lines (BLs); and N BL break nodes, each being configured to separate a corresponding one of the BLs into a first BL pin and a second BL pin, wherein the M and the N each are a positive even number.

Embodiments of the present application provide a memory array circuit, a memory array layout and a verification method. The memory array circuit includes: M word lines (WLs); M WL break nodes, each being configured to separate a corresponding one of the WLs into a first WL pin and a second WL pin; N bit lines (BLs); and N BL break nodes, each being configured to separate a corresponding one of the BLs into a first BL pin and a second BL pin, wherein the M and the N each are a positive even number.

An integrated circuit includes a plurality of standard cells including first and second standard cells arranged adjacent to each other in a first direction, and first, second, and third metal layers sequentially stacked in a vertical direction. At least one power segment is arranged adjacent a region where at least one of the first standard cell and the second standard cell is arranged. The at least one power segment is configured to provide power to the plurality of standard cells and is formed as a pattern of the third metal layer extending in a second direction.

An integrated circuit includes a plurality of standard cells including first and second standard cells arranged adjacent to each other in a first direction, and first, second, and third metal layers sequentially stacked in a vertical direction. At least one power segment is arranged adjacent a region where at least one of the first standard cell and the second standard cell is arranged. The at least one power segment is configured to provide power to the plurality of standard cells and is formed as a pattern of the third metal layer extending in a second direction.

Approaches for placing logic of a circuit design include determining respective relative activation rates of control paths in a high-level language (HLL) program by a design tool. The HLL program specifies a circuit design. The design tool compiles the HLL program into logic functions and determines respective relative activation rates of signal connections between the logic functions based on the relative activation rates of the control paths in the HLL program. The design tool selects placement locations on an integrated circuit device for the logic functions using a placement cost minimization function that factors the relative activation rates of the signal connections into placement costs.

A simulator can simulate a circuit design describing an electronic device using a single processing device of a computing system. The simulator can generate profile data associated with compilation of the circuit design and the single processing device simulation of the compiled circuit design. The profile data can identify multiple different ways to partition the circuit design and include information corresponding to the single processing device simulation of the compiled circuit design. A parallel simulation qualifier can determine a parallelism factor corresponding to an expected performance of the computing system in a multiple processing device simulation of the circuit design based on the profile data from the single processing device simulation of the circuit design. The simulator can utilize the parallelism factor to partition the circuit design in one of the different ways, and simulate the partitioned circuit design with multiple processing devices of the computing system.

Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.

Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.

A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.