A method and an apparatus of designing an integrated circuit are provided. The method includes: S1, loading a power fill to a circuit layout with original metal lines; S2, checking whether a current layout includes a region with a spacing error; if yes, performing S3; otherwise, outputting the current layout; and S3, pruning a power fill shape corresponding to the region with a spacing error by a predetermined spacing width delta, and returning to the S2.

A method for identifying a latch-up structure includes the following operations. In a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in an N-well is found. A second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-type substrate is found. A second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the N-well is found, the N-well is located on the P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well, and the P-type substrate is identified as the latch-up structure.

The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving one or more user defined processor configurations at a processor generator. Embodiments may also include generating a customized testbench based upon, at least in part, the user defined processor configurations and generating an RTL model while the customized testbench is generating.

The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving one or more user defined processor configurations at a processor generator. Embodiments may also include generating a customized testbench based upon, at least in part, the user defined processor configurations and generating an RTL model while the customized testbench is generating.

A method for analyzing an analog circuit controlled by a plurality of digital inputs is presented. The circuit is represented with a data structure with nodes connected via edges, which represent a circuit component. The data structure can be traversed across all connected nodes; and said digital inputs can be toggled between two or more input states. The method steps include identifying a set of boundary nodes in the data structure which are at a digital-analog boundary of the data structure; for each digital input, identifying associated boundary nodes which are coupled with the digital input; grouping digital inputs into input sets, where each of the different input sets are associated with mutually exclusive sets of associated boundary nodes, and analyzing the circuit by successively analyzing one or more of the input sets for all possible combinations of inputs states within that set.

A method for analyzing an analog circuit controlled by a plurality of digital inputs is presented. The circuit is represented with a data structure with nodes connected via edges, which represent a circuit component. The data structure can be traversed across all connected nodes; and said digital inputs can be toggled between two or more input states. The method steps include identifying a set of boundary nodes in the data structure which are at a digital-analog boundary of the data structure; for each digital input, identifying associated boundary nodes which are coupled with the digital input; grouping digital inputs into input sets, where each of the different input sets are associated with mutually exclusive sets of associated boundary nodes, and analyzing the circuit by successively analyzing one or more of the input sets for all possible combinations of inputs states within that set.

To increase the efficiency of an electronic design automation (EDA) process, for a putative integrated circuit design for which computerized routing is to be carried out within an EDA program, run a sweep line algorithm selectively on active metal shapes in said putative design for different layers, to determine a total number of said active metal shapes, and compute a memory requirement for computerized routing on said active shapes based on said total number of said active shapes. For said putative design, compute a memory requirement for computerized routing on inactive metal shapes based on a total number of said inactive shapes; partition said putative design into a plurality of partitions, based on said memory requirement for computerized routing on said active and inactive shapes, such that an available system memory is not exceeded. Separately run a routing job on each of said plurality of partitions.

To increase the efficiency of an electronic design automation (EDA) process, for a putative integrated circuit design for which computerized routing is to be carried out within an EDA program, run a sweep line algorithm selectively on active metal shapes in said putative design for different layers, to determine a total number of said active metal shapes, and compute a memory requirement for computerized routing on said active shapes based on said total number of said active shapes. For said putative design, compute a memory requirement for computerized routing on inactive metal shapes based on a total number of said inactive shapes; partition said putative design into a plurality of partitions, based on said memory requirement for computerized routing on said active and inactive shapes, such that an available system memory is not exceeded. Separately run a routing job on each of said plurality of partitions.

A constraint graph for a candidate routing solution is created; each node in the graph represents a position of an end of a metal shape and each arc in the graph represents a design rule constraint between two of the nodes. A solution graph is computed, for at least a portion of the constraint graph, using a shape processing algorithm. The solution graph is checked for design rule violations to generate one or more violation graphs. A constraint window and a selection of one or more arcs for at least one of the violation graphs are generated. The candidate routing solution is revised, based on one or more violated design rules corresponding to at least one of the selected arcs within the constraint window. Optionally, an integrated circuit is fabricated in accordance with the revised solution.

A constraint graph for a candidate routing solution is created; each node in the graph represents a position of an end of a metal shape and each arc in the graph represents a design rule constraint between two of the nodes. A solution graph is computed, for at least a portion of the constraint graph, using a shape processing algorithm. The solution graph is checked for design rule violations to generate one or more violation graphs. A constraint window and a selection of one or more arcs for at least one of the violation graphs are generated. The candidate routing solution is revised, based on one or more violated design rules corresponding to at least one of the selected arcs within the constraint window. Optionally, an integrated circuit is fabricated in accordance with the revised solution.