An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

A method, computer system, and computer program product of performing a matrix convolution on a multidimensional input matrix for obtaining a multidimensional output matrix. The matrix convolution may include a set of dot product operations for obtaining all elements of the output matrix. Each dot product operation of the set of dot product operations may include an input submatrix of the input matrix and at least one convolution matrix. The method may include providing a memristive crossbar array configured to perform a vector matrix multiplication. A subset of the set of dot product operations may be computed by storing the convolution matrices of the subset of dot product operations in the crossbar array and inputting to the crossbar array one input vector comprising all distinct elements of the input submatrices of the subset.

A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by performing computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

An apparatus is disclosed, comprising means for providing in an integrated circuit a resistive network comprising a first resistance element having a first resistance value and a second resistance element having a second resistance value, each resistance element of the resistive network being provided by one or more high-resistance contacts between conductors of the integrated circuit. The apparatus may also provide a means for providing in the integrated circuit an electrical current from the resistive network to one of a summing node output and a subtraction node output for input to a corresponding summing node input and a subtraction node input of a signal processing component. A method for forming such an integrated circuit is also disclosed.

According to one embodiment, an arithmetic device includes an arithmetic circuit. The arithmetic circuit includes a memory part including a plurality of memory regions, and an arithmetic part. One of the memory regions includes a capacitance including a first terminal, and a first electrical circuit electrically connected to the first terminal and configured to output a voltage signal corresponding to a potential of the first terminal.

An arithmetic apparatus according to an embodiment outputs a multiplicative value obtained by multiplying a weight value and an input value. The arithmetic apparatus includes a memristor, a logarithmic transform circuit, and a current-voltage converter circuit. The memristor is a device capable of changing voltage-current characteristic, and the memristor is preset to voltage-current characteristic according to the weight value. The logarithmic transform circuit applies an intermediate voltage, to the memristor, that is obtained by logarithmically transforming an input voltage according to the input value in accordance with a logarithmic transform function obtained by multiplying a natural logarithm function by a preset coefficient. The current-voltage converter circuit outputs an output voltage obtained by performing current-voltage conversion of current flowing through the memristor according to a preset linear function, as a multiplicative value.

A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by perform computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Hardware for speeding up MCMC is realized. An information processing apparatus includes a plurality of Ising chips and a controller that controls the plurality of Ising chips. Each of the plurality of Ising chips includes a plurality of units, and each of the plurality of units retains a spin state. The controller instructs one set of Ising chips among the plurality of Ising chips to compare values of spin states of corresponding units and instructs the one set of Ising chip to invert values of a portion of spins among spins having different values of spin states of the corresponding units.

A circuit for performing energy-efficient and high-throughput multiply-accumulate (MAC) arithmetic dot-product operations and convolution computations includes a two dimensional crossbar array comprising a plurality of row inputs and at least one column having a plurality of column circuits, wherein each column circuit is coupled to a respective row input. Each respective column circuit includes an excitatory memristor neuron circuit having an input coupled to a respective row input, a first synapse circuit coupled to an output of the excitatory memristor neuron circuit, the first synapse circuit having a first output, an inhibitory memristor neuron circuit having an input coupled to the respective row input, and a second synapse circuit coupled to an output of the inhibitory memristor neuron circuit, the second synapse circuit having a second output. An output memristor neuron circuit is coupled to the first output and second output of each column circuit and has an output.