Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.

Methods, systems, and devices for spare substitution in a memory system are described. Aspects include a memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.

The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.

According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The configuration unit assigns write management areas included in a nonvolatile memory to spaces and an input space. The write management area is a unit of an area which manages the number of write. The address translation unit associates a logical address of write data with a physical address which indicates a position of the write data in the nonvolatile memory. The write unit writes the write data to the input space and then writes the write data in the input space to a space corresponding to the write data amongst the spaces. The control unit controls the spaces individually with respect to the nonvolatile memory.

A memory system includes: a memory block including a plurality of pages each comprising a plurality of memory cells connected to bit lines and a word line of word lines, an address manager configured to output addresses corresponding to the plurality of pages, and a system data manager configured to generate index data corresponding to the each of the addresses, the index data indicating whether user data is inverted, and output the index data and information on a memory cell in which the index data is to be stored, respectively. The system data manager is configured to, determine memory cells connected to different bit lines from among memory cells included in adjacent pages corresponding to consecutive addresses of the addresses, as memory cells in which index data corresponding to the consecutive addresses are to be stored.

An operation method for a memory system may include: an accessing a plurality of memory devices, each including a plurality of dies, in an interleaving manner, and performing program operations; and performing at least one internal read operation to read data from the plurality of dies accessed in the interleaving manner, during the program operations, wherein one or more internal read operations which are performed during any one program operation of the program operations are determined according to a maximum internal read operation number and a minimum internal read operation waiting number.

An example method may include performing a first wear leveling operation on a group of data blocks based on a write counter associated with the group of data blocks, wherein the first wear leveling operation comprises including the group of data blocks in a plurality of groups of mapped data blocks, responsive to including the group of data blocks in the plurality of groups of mapped data blocks, performing a second wear leveling operation on the group of data blocks, wherein performing the second wear leveling operation comprises determining a base address of the group of data blocks, the base address indicating a location at which the group of data blocks begins, and accessing a data block in the group of data blocks based on the base address of the group of data blocks and a logical address associated with the data block.

A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is configured to communicate with an NVM. The processor is configured to store in the NVM Type-Length-Value (TLV) records, each TLV record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least respective validity indicators of the TLV records, to read the TLV records that include the encrypted fields and the non-encrypted fields from the NVM, and to invalidate selected TLV records by modifying the respective validity indicators of the selected TLV records that are stored in the non-encrypted fields.

A method includes obtaining an average number of valid pages per block of the solid state storage device, obtaining an average number of invalid pages per block of the solid state storage device, determining a scaling factor as a function of the a number of free blocks in the solid state storage device, a steady state target number of free blocks, a high target number of free blocks, and a low target number of free blocks, and applying the scaling factor to the average number of invalid pages to control a ratio of host writes versus garbage collection writes to the solid state storage device.

A first size set in a case where a first request including at least discard processing is received from a first application is wider than a second size set in a case where a second request including at least the discard processing is received from a second application different from the first application.