An apparatus is described. The apparatus includes a non volatile memory module for insertion into a rack implemented modular computer. The non volatile memory module includes a plurality of memory controllers. The non volatile memory includes respective non-volatile random access memory coupled to each of the memory controllers. The non volatile memory module includes a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers. The incoming requests are sent by one or more CPU modules of the rack implemented modular computer. The outgoing responses are sent to the one or more CPU modules.

A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol

Various embodiments comprise devices and methods to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the device is to manage logical memory partitioning on each of multiple memory devices that are based on differing, hybrid-memory technologies, the device is further to hide an actual storage media type of the multiple memory devices from the host through abstracted logical interface blocks. Additional devices and methods are described.

Disclosed herein are system, method, and computer program product embodiments for of big block allocation of persistent main memory. An embodiment operates by receiving an allocation request for memory of a requested size. A free memory block, that exceeds the requested size by a remainder and is available for allocation, is determined. A size of the free memory block is updated to indicate that the size of the free memory block is equal to the remainder size. A new block of the requested size is inserted with an indication that the new block is allocated. A memory address corresponding to the new block is returned.

Disclosed herein are system, method, and computer program product embodiments for of big block allocation of persistent main memory. An embodiment operates by receiving an allocation request for memory of a requested size. A free memory block, that exceeds the requested size by a remainder and is available for allocation, is determined. A size of the free memory block is updated to indicate that the size of the free memory block is equal to the remainder size. A new block of the requested size is inserted with an indication that the new block is allocated. A memory address corresponding to the new block is returned.

A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.

Methods and systems for managing memory and stress to memory systems. A method for managing memory includes receiving from a software application memory retention requirements for application data. The memory retention requirements include storage duration length and/or criticality of data retention. The method also includes storing the application data in one of a plurality of memory regions in non-volatile memory based on the memory retention requirements and memory retention characteristics of the memory regions. Each memory region may have different memory retention characteristics.

A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

A server apparatus includes a reception unit that receives, from a client apparatus, an updated data acquisition request for acquisition of updated data on setting information about the client apparatus that is stored in a non-volatile storage device of the server apparatus, a generation unit that generates data indicating that the updated data does not exist without accessing the non-volatile storage device in a case where identification information for identifying the client apparatus that transmitted the updated data acquisition request is included in an identification information list of a client to which an updated data response has been transmitted, the identification information list being stored in a cache memory, and a response unit that transmits to the client apparatus a response with the generated data indicating that the updated data does not exist.