A data accessing device to access a storage element that stores encrypted data is provided. The data accessing device includes a processing circuit, a storage controller, a decrypting circuit and a combinational logic circuit. The processing circuit generates an accessing address and decryption related information according to an accessing command. The storage controller receives the accessing address and accesses corresponding encrypted data accordingly. The decrypting circuit receives the decryption related information and a pre-stored key to generate a decrypting cipher accordingly. The combinational logic circuit receives the corresponding encrypted data and the decrypting cipher to perform a logic operation to generate decrypted data accordingly that enables the processing circuit to access the decrypted data.

A one-time programmable (OTP) memory has a plurality of pages. A predefined section of each page is configured to store error policy bits. When an indicator in a first predefined location has a first value, the page is configured to store data with error correction code (ECC) bits, and when the indicator has a second value, at least a portion of the page is configured to store data with redundancy. Address translation circuitry is configured to, in response to receiving an access address, use a second predefined location of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.

An integrated circuit includes a one-time programmable (OTP) memory having a plurality of pages and address translation circuitry. A first line of each page is configured to store error policy bits. When a first bit of the first line has a first value, the page is configured to store data with error correction code (ECC) bits, and when the first bit has a second value, at least a portion of the page is configured to store data with redundancy. The address translation circuitry is configured to, in response to receiving an access address, use the first line of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.

An integrated circuit includes a one-time programmable (OTP) memory having a plurality of pages and address translation circuitry. A first line of each page is configured to store error policy bits. When a first bit of the first line has a first value, the page is configured to store data with error correction code (ECC) bits, and when the first bit has a second value, at least a portion of the page is configured to store data with redundancy. The address translation circuitry is configured to, in response to receiving an access address, use the first line of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.

A method and/or system for providing for write once read many (WORM) times from at least some addresses of a storage drive that is otherwise manufactured for multiple writes to individual addresses. In at least one embodiment, a WORM area(s) is defined by a START_LBA and an END_LBA and the method uses a HWM_LBA to determine whether a LBA in the WORM area has been written to previously and to prevent previously written to LBA(s) in the WORM area from being rewritten. In at least one embodiment where there are multiple WORM areas, each WORM area has its own respective START_LBA, END_LBA and HWM_LBA.

A method and/or system for providing for write once read many (WORM) times from at least some addresses of a storage drive that is otherwise manufactured for multiple writes to individual addresses. In at least one embodiment, a WORM area(s) is defined by a START_LBA and an END_LBA and the method uses a HWM_LBA to determine whether a LBA in the WORM area has been written to previously and to prevent previously written to LBA(s) in the WORM area from being rewritten. In at least one embodiment where there are multiple WORM areas, each WORM area has its own respective START_LBA, END_LBA and HWM_LBA.

A method and apparatus for executing an application program stored in an one-time-programmable, OTP, memory in a system on chip (SoC) is described. The SoC has RAM, a CPU and an OTP controller. The OTP memory stores an application program. The method includes, by the processor unit at power-up, instructing the OTP controller to copy the application program from the OTP memory to RAM, executing the application program from RAM, and setting the system on chip (SoC) in sleep mode. By the OTP controller after a wake-up, copying the application program from the OTP memory to the RAM and after the copying, waking up the CPU and transferring control back to the CPU. By the CPU after being woken up by the OTP controller, executing the application program from RAM.