A one-time programmable (OTP) memory has a plurality of pages. A predefined section of each page is configured to store error policy bits. When an indicator in a first predefined location has a first value, the page is configured to store data with error correction code (ECC) bits, and when the indicator has a second value, at least a portion of the page is configured to store data with redundancy. Address translation circuitry is configured to, in response to receiving an access address, use a second predefined location of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.

A one-time programmable memory device is provided in the invention. The one-time programmable memory device includes a one-time programmable memory and a memory controller. The one-time programmable memory includes a first block, a second block and a third block. The first block includes a plurality of initial-address-unit groups and each initial-address-unit group includes a plurality of initial address units and each initial address unit corresponds to a variable to record the storage address of its corresponding variable. The second block includes a plurality of initial address control units and each initial address control unit corresponds to one of the variables to record the corresponding initial-address-unit group of each variable. The third block includes a plurality of storage units and each storage unit has a corresponding storage address. The memory controller is configured to assign the storage addresses to the variables.

A secure read-only-memory (ROM) code patching system includes a processor that is configured to generate first partial cryptographic data based on a ROM patch and a set of secret bits, and authenticate the ROM patch based on a match between the first partial cryptographic data and reference partial cryptographic data of the ROM patch. Upon the authentication of the ROM patch, the processor is further configured to generate an address associated with a set of ROM instructions of a ROM code. Based on a match between the generated address and a ROM patch address of the ROM patch, the processor is further configured to execute a set of patch instructions of the ROM patch that is successfully authenticated instead of the set of ROM instructions, thereby securely patching the ROM code.

A secure read-only-memory (ROM) code patching system includes a processor that is configured to generate first partial cryptographic data based on a ROM patch and a set of secret bits, and authenticate the ROM patch based on a match between the first partial cryptographic data and reference partial cryptographic data of the ROM patch. Upon the authentication of the ROM patch, the processor is further configured to generate an address associated with a set of ROM instructions of a ROM code. Based on a match between the generated address and a ROM patch address of the ROM patch, the processor is further configured to execute a set of patch instructions of the ROM patch that is successfully authenticated instead of the set of ROM instructions, thereby securely patching the ROM code.

A data accessing device to access a storage element that stores encrypted data is provided. The data accessing device includes a processing circuit, a storage controller, a decrypting circuit and a combinational logic circuit. The processing circuit generates an accessing address and decryption related information according to an accessing command. The storage controller receives the accessing address and accesses corresponding encrypted data accordingly. The decrypting circuit receives the decryption related information and a pre-stored key to generate a decrypting cipher accordingly. The combinational logic circuit receives the corresponding encrypted data and the decrypting cipher to perform a logic operation to generate decrypted data accordingly that enables the processing circuit to access the decrypted data.

A one-time programmable memory device is provided in the invention. The one-time programmable memory device includes a one-time programmable memory and a memory controller. The one-time programmable memory includes a first block, a second block and a third block. The first block includes a plurality of initial-address-unit groups and each initial-address-unit group includes a plurality of initial address units and each initial address unit corresponds to a variable to record the storage address of its corresponding variable. The second block includes a plurality of initial address control units and each initial address control unit corresponds to one of the variables to record the corresponding initial-address-unit group of each variable. The third block includes a plurality of storage units and each storage unit has a corresponding storage address. The memory controller is configured to assign the storage addresses to the variables.

A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.

A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.

Embodiments include method, systems and computer program products for operating a resettable write once read many (RWORM) memory. The method includes receiving, by a processor, a request for at least a portion of memory in a computer system to be designated as RWORM memory. The processor further writes data to the RWORM memory. The processor further maintains the RWORM memory in a read-only state after the RWORM memory is written to. The processor further re-designates the RWORM memory to a read/write state in response to encountering a system reset.

Embodiments include method, systems and computer program products for operating a resettable write once read many (RWORM) memory. The method includes receiving, by a processor, a request for at least a portion of memory in a computer system to be designated as RWORM memory. The processor further writes data to the RWORM memory. The processor further maintains the RWORM memory in a read-only state after the RWORM memory is written to. The processor further re-designates the RWORM memory to a read/write state in response to encountering a system reset.