Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI.

Disclosed herein includes a system, a method, and a device for reading and writing sparse data in a neural network accelerator. A mask identifying byte positions within a data word having non-zero values in memory can be accessed. Each bit of the mask can have a first value or a second value, the first value indicating that a byte of the data word corresponds to a non-zero byte value, the second value indicating that the byte of the data word corresponds to a zero byte value. The data word can be modified to have non-zero byte values stored at an end of a first side of the data word in the memory, and any zero byte values stored in a remainder of the data word. The modified data word can be written to the memory via at least a first slice of a plurality of slices that is configured to access the first side of the data word in the memory.

Provided is a method for optimising memory writing in a device implementing a cryptography module and a client module calling functions implemented by the cryptography module. The device includes a random access memory including a first memory zone that is secured and dedicated to the cryptography module and a second memory zone dedicated to the client module. When the client module calls a series of functions implemented by the cryptography module including a first function and at least one second function, with each second function executed following the first function or from a further second function and providing a runtime result added to a runtime result of the preceding series function, each runtime result is added to a value contained in a buffer memory allocated in the first memory. The buffer memory value is copied to the second memory zone following the execution of the last function of the series.

A method includes deploying non-volatile random access memory (NVRAM) coupled to a processor or central processing unit (CPU) core of a computing device as a peripheral device via an input/output (I/O) bus, and providing a NVRAM application programming interface (API) for the CPU core to conduct NVRAM read and write operations. Providing the NVRAM API includes allocating a single memory buffer per command to hold data transferred to or from the NVRAM. The method includes configuring the processor in conjunction with the NVRAM API to set up command queues inside in the host Memory Mapped Input Output (MMIO) space.

Systems, methods, and computer readable storage mediums for maintaining the history of remapped data in a storage system. A first portion of a first medium may be remapped to a second medium as part of read optimization operations, wherein the second medium is younger than the first medium. A tag associated with the first portion of the first medium may be retained when the first portion is remapped to the second medium. When the second medium is replicated to another storage array, the first portion of the first medium may be prevented from being replicated based on the tag identifying the first portion as being part of a previous replication operation.

Examples relate to a memory controller or memory controller device for a memory pool of a computer system, to a management apparatus or management device for the computer system, and to an apparatus or device for a compute node of the computer system, and to corresponding methods and computer programs. The memory pool comprises computer memory that is accessible to a plurality of compute nodes of the computer system via the memory controller. The memory controller comprises interface circuitry for communicating with the plurality of compute nodes. The memory controller comprises control circuitry being configured to obtain an access control instruction via the interface circuitry. The access control instruction indicates that access to a portion of the computer memory of the memory pool is to be granted to one or more processes being executed by the plurality of compute nodes of the computer system. The access control instruction comprises information related to a node identifier and a process identifier for each of the one or more processes. The control circuitry is configured to provide access to the portion of the computer memory of the memory pool to the one or more processes based on the access control instruction.

Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.

Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.